include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_DEEP_SLEEP
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #define CONFIG_SYS_CLK_FREQ             100000000
  18
  19 #define DDR_SDRAM_CFG                   0x470c0008
  20 #define DDR_CS0_BNDS                    0x008000bf
  21 #define DDR_CS0_CONFIG                  0x80014302
  22 #define DDR_TIMING_CFG_0                0x50550004
  23 #define DDR_TIMING_CFG_1                0xbcb38c56
  24 #define DDR_TIMING_CFG_2                0x0040d120
  25 #define DDR_TIMING_CFG_3                0x010e1000
  26 #define DDR_TIMING_CFG_4                0x00000001
  27 #define DDR_TIMING_CFG_5                0x03401400
  28 #define DDR_SDRAM_CFG_2                 0x00401010
  29 #define DDR_SDRAM_MODE                  0x00061c60
  30 #define DDR_SDRAM_MODE_2                0x00180000
  31 #define DDR_SDRAM_INTERVAL              0x18600618
  32 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  33 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  34 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  35 #define DDR_DDR_CDR1                    0x80040000
  36 #define DDR_DDR_CDR2                    0x00000001
  37 #define DDR_SDRAM_CLK_CNTL              0x02000000
  38 #define DDR_DDR_ZQ_CNTL                 0x89080600
  39 #define DDR_CS0_CONFIG_2                0
  40 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  41 #define SDRAM_CFG2_D_INIT               0x00000010
  42 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  43 #define SDRAM_CFG2_FRC_SR               0x80000000
  44 #define SDRAM_CFG_BI                    0x00000001
  45
  46 #ifdef CONFIG_SD_BOOT
  47 #ifdef CONFIG_NXP_ESBC
  48 /*
  49  * HDR would be appended at end of image and copied to DDR along
  50  * with U-Boot image.
  51  */
  52 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  53 #endif /* ifdef CONFIG_NXP_ESBC */
  54
  55 #define CONFIG_SPL_MAX_SIZE             0x1a000
  56 #define CONFIG_SPL_STACK                0x1001d000
  57 #define CONFIG_SPL_PAD_TO               0x1c000
  58
  59 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  60                 CONFIG_SYS_MONITOR_LEN)
  61 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  62 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  63 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  64
  65 #ifdef CONFIG_U_BOOT_HDR_SIZE
  66 /*
  67  * HDR would be appended at end of image and copied to DDR along
  68  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  69  * size increases then increase this size in case of secure boot as
  70  * it uses raw u-boot image instead of fit image.
  71  */
  72 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  73 #else
  74 #define CONFIG_SYS_MONITOR_LEN          0x100000
  75 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  76 #endif
  77
  78 #define PHYS_SDRAM                      0x80000000
  79 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  80
  81 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  82 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  83
  84 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  85
  86 /*
  87  * IFC Definitions
  88  */
  89 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  90 #define CONFIG_SYS_FLASH_BASE           0x60000000
  91 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  92
  93 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  94 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  95                                 CSPR_PORT_SIZE_16 | \
  96                                 CSPR_MSEL_NOR | \
  97                                 CSPR_V)
  98 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  99
 100 /* NOR Flash Timing Params */
 101 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 102                                         CSOR_NOR_TRHZ_80)
 103 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 104                                         FTIM0_NOR_TEADC(0x5) | \
 105                                         FTIM0_NOR_TAVDS(0x0) | \
 106                                         FTIM0_NOR_TEAHC(0x5))
 107 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 108                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 109                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 110 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 111                                         FTIM2_NOR_TCH(0x4) | \
 112                                         FTIM2_NOR_TWP(0x1c) | \
 113                                         FTIM2_NOR_TWPH(0x0e))
 114 #define CONFIG_SYS_NOR_FTIM3            0
 115
 116 #define CONFIG_SYS_FLASH_QUIET_TEST
 117 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 118
 119 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 120 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 121 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 122 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 123
 124 #define CONFIG_SYS_FLASH_EMPTY_INFO
 125 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 126
 127 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 128 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 129 #endif
 130
 131 /* CPLD */
 132
 133 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 134 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 135
 136 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 137 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 138                                         CSPR_PORT_SIZE_8 | \
 139                                         CSPR_MSEL_GPCM | \
 140                                         CSPR_V)
 141 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 142 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 143                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 144                                         CSOR_NOR_TRHZ_80)
 145
 146 /* CPLD Timing parameters for IFC GPCM */
 147 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 148                                         FTIM0_GPCM_TEADC(0xf) | \
 149                                         FTIM0_GPCM_TEAHC(0xf))
 150 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 151                                         FTIM1_GPCM_TRAD(0x3f))
 152 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 153                                         FTIM2_GPCM_TCH(0xf) | \
 154                                         FTIM2_GPCM_TWP(0xff))
 155 #define CONFIG_SYS_FPGA_FTIM3           0x0
 156 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 157 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 158 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 159 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 160 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 161 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 162 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 163 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 164 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 165 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 166 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 167 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 168 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 169 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 170 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 171 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 172
 173 /*
 174  * Serial Port
 175  */
 176 #ifdef CONFIG_LPUART
 177 #define CONFIG_LPUART_32B_REG
 178 #else
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #ifndef CONFIG_DM_SERIAL
 181 #define CONFIG_SYS_NS16550_REG_SIZE     1
 182 #endif
 183 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 184 #endif
 185
 186 /*
 187  * I2C
 188  */
 189
 190 /* GPIO */
 191
 192 /* EEPROM */
 193 #define CONFIG_SYS_I2C_EEPROM_NXID
 194 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 195
 196 /*
 197  * MMC
 198  */
 199
 200 /*
 201  * Video
 202  */
 203 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 204 #define CONFIG_VIDEO_LOGO
 205 #define CONFIG_VIDEO_BMP_LOGO
 206
 207 #define CONFIG_FSL_DCU_SII9022A
 208 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 209 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 210 #endif
 211
 212 /*
 213  * eTSEC
 214  */
 215
 216 #ifdef CONFIG_TSEC_ENET
 217 #define CONFIG_ETHPRIME                 "ethernet@2d10000"
 218 #endif
 219
 220 /* PCIe */
 221 #define CONFIG_PCIE1            /* PCIE controller 1 */
 222 #define CONFIG_PCIE2            /* PCIE controller 2 */
 223
 224 #ifdef CONFIG_PCI
 225 #define CONFIG_PCI_SCAN_SHOW
 226 #endif
 227
 228 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 229 #define CONFIG_LAYERSCAPE_NS_ACCESS
 230 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 231 #define COUNTER_FREQUENCY               12500000
 232
 233 #define CONFIG_HWCONFIG
 234 #define HWCONFIG_BUFFER_SIZE            256
 235
 236 #define CONFIG_FSL_DEVICE_DISABLE
 237
 238 #define BOOT_TARGET_DEVICES(func) \
 239         func(MMC, mmc, 0) \
 240         func(USB, usb, 0) \
 241         func(DHCP, dhcp, na)
 242 #include <config_distro_bootcmd.h>
 243
 244 #ifdef CONFIG_LPUART
 245 #define CONFIG_EXTRA_ENV_SETTINGS       \
 246         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 247                 "cma=64M@0x0-0xb0000000\0" \
 248         "initrd_high=0xffffffff\0"      \
 249         "fdt_addr=0x64f00000\0"         \
 250         "kernel_addr=0x65000000\0"      \
 251         "scriptaddr=0x80000000\0"       \
 252         "scripthdraddr=0x80080000\0"    \
 253         "fdtheader_addr_r=0x80100000\0" \
 254         "kernelheader_addr_r=0x80200000\0"      \
 255         "kernel_addr_r=0x81000000\0"    \
 256         "fdt_addr_r=0x90000000\0"       \
 257         "ramdisk_addr_r=0xa0000000\0"   \
 258         "load_addr=0xa0000000\0"        \
 259         "kernel_size=0x2800000\0"       \
 260         "kernel_addr_sd=0x8000\0"       \
 261         "kernel_size_sd=0x14000\0"      \
 262         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 263         BOOTENV                         \
 264         "boot_scripts=ls1021atwr_boot.scr\0"    \
 265         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 266                 "scan_dev_for_boot_part="       \
 267                         "part list ${devtype} ${devnum} devplist; "     \
 268                         "env exists devplist || setenv devplist 1; "    \
 269                         "for distro_bootpart in ${devplist}; do "       \
 270                         "if fstype ${devtype} "                         \
 271                                 "${devnum}:${distro_bootpart} "         \
 272                                 "bootfstype; then "                     \
 273                                 "run scan_dev_for_boot; "               \
 274                         "fi; "                  \
 275                 "done\0"                        \
 276         "scan_dev_for_boot="                              \
 277                 "echo Scanning ${devtype} "               \
 278                                 "${devnum}:${distro_bootpart}...; "  \
 279                 "for prefix in ${boot_prefixes}; do "     \
 280                         "run scan_dev_for_scripts; "      \
 281                 "done;"                                   \
 282                 "\0"                                      \
 283         "boot_a_script="                                  \
 284                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 285                         "${scriptaddr} ${prefix}${script}; "    \
 286                 "env exists secureboot && load ${devtype} "     \
 287                         "${devnum}:${distro_bootpart} "         \
 288                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 289                         "env exists secureboot "        \
 290                         "&& esbc_validate ${scripthdraddr};"    \
 291                 "source ${scriptaddr}\0"          \
 292         "installer=load mmc 0:2 $load_addr "    \
 293                 "/flex_installer_arm32.itb; "           \
 294                 "bootm $load_addr#ls1021atwr\0" \
 295         "qspi_bootcmd=echo Trying load from qspi..;"    \
 296                 "sf probe && sf read $load_addr "       \
 297                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 298         "nor_bootcmd=echo Trying load from nor..;"      \
 299                 "cp.b $kernel_addr $load_addr "         \
 300                 "$kernel_size && bootm $load_addr#$board\0"
 301 #else
 302 #define CONFIG_EXTRA_ENV_SETTINGS       \
 303         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 304                 "cma=64M@0x0-0xb0000000\0" \
 305         "initrd_high=0xffffffff\0"      \
 306         "fdt_addr=0x64f00000\0"         \
 307         "kernel_addr=0x61000000\0"      \
 308         "kernelheader_addr=0x60800000\0"        \
 309         "scriptaddr=0x80000000\0"       \
 310         "scripthdraddr=0x80080000\0"    \
 311         "fdtheader_addr_r=0x80100000\0" \
 312         "kernelheader_addr_r=0x80200000\0"      \
 313         "kernel_addr_r=0x81000000\0"    \
 314         "kernelheader_size=0x40000\0"   \
 315         "fdt_addr_r=0x90000000\0"       \
 316         "ramdisk_addr_r=0xa0000000\0"   \
 317         "load_addr=0xa0000000\0"        \
 318         "kernel_size=0x2800000\0"       \
 319         "kernel_addr_sd=0x8000\0"       \
 320         "kernel_size_sd=0x14000\0"      \
 321         "kernelhdr_addr_sd=0x4000\0"            \
 322         "kernelhdr_size_sd=0x10\0"              \
 323         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 324         BOOTENV                         \
 325         "boot_scripts=ls1021atwr_boot.scr\0"    \
 326         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 327                 "scan_dev_for_boot_part="       \
 328                         "part list ${devtype} ${devnum} devplist; "     \
 329                         "env exists devplist || setenv devplist 1; "    \
 330                         "for distro_bootpart in ${devplist}; do "       \
 331                         "if fstype ${devtype} "                         \
 332                                 "${devnum}:${distro_bootpart} "         \
 333                                 "bootfstype; then "                     \
 334                                 "run scan_dev_for_boot; "               \
 335                         "fi; "                  \
 336                 "done\0"                        \
 337         "scan_dev_for_boot="                              \
 338                 "echo Scanning ${devtype} "               \
 339                                 "${devnum}:${distro_bootpart}...; "  \
 340                 "for prefix in ${boot_prefixes}; do "     \
 341                         "run scan_dev_for_scripts; "      \
 342                 "done;"                                   \
 343                 "\0"                                      \
 344         "boot_a_script="                                  \
 345                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 346                         "${scriptaddr} ${prefix}${script}; "    \
 347                 "env exists secureboot && load ${devtype} "     \
 348                         "${devnum}:${distro_bootpart} "         \
 349                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 350                         "&& esbc_validate ${scripthdraddr};"    \
 351                 "source ${scriptaddr}\0"          \
 352         "qspi_bootcmd=echo Trying load from qspi..;"    \
 353                 "sf probe && sf read $load_addr "       \
 354                 "$kernel_addr $kernel_size; env exists secureboot "     \
 355                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 356                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 357                 "bootm $load_addr#$board\0" \
 358         "nor_bootcmd=echo Trying load from nor..;"      \
 359                 "cp.b $kernel_addr $load_addr "         \
 360                 "$kernel_size; env exists secureboot "  \
 361                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 362                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 363                 "bootm $load_addr#$board\0"     \
 364         "sd_bootcmd=echo Trying load from SD ..;"       \
 365                 "mmcinfo && mmc read $load_addr "       \
 366                 "$kernel_addr_sd $kernel_size_sd && "   \
 367                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 368                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 369                 " && esbc_validate ${kernelheader_addr_r};"     \
 370                 "bootm $load_addr#$board\0"
 371 #endif
 372
 373 /*
 374  * Miscellaneous configurable options
 375  */
 376 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 377
 378 #define CONFIG_LS102XA_STREAM_ID
 379
 380 #define CONFIG_SYS_INIT_SP_OFFSET \
 381         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 382 #define CONFIG_SYS_INIT_SP_ADDR \
 383         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 384
 385 #ifdef CONFIG_SPL_BUILD
 386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 387 #else
 388 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 389 #endif
 390
 391 /*
 392  * Environment
 393  */
 394
 395 #include <asm/fsl_secure_boot.h>
 396 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 397
 398 #endif