include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_DEEP_SLEEP
  15
  16 /*
  17  * Size of malloc() pool
  18  */
  19 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  20
  21 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  22 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  23
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25
  26 #define DDR_SDRAM_CFG                   0x470c0008
  27 #define DDR_CS0_BNDS                    0x008000bf
  28 #define DDR_CS0_CONFIG                  0x80014302
  29 #define DDR_TIMING_CFG_0                0x50550004
  30 #define DDR_TIMING_CFG_1                0xbcb38c56
  31 #define DDR_TIMING_CFG_2                0x0040d120
  32 #define DDR_TIMING_CFG_3                0x010e1000
  33 #define DDR_TIMING_CFG_4                0x00000001
  34 #define DDR_TIMING_CFG_5                0x03401400
  35 #define DDR_SDRAM_CFG_2                 0x00401010
  36 #define DDR_SDRAM_MODE                  0x00061c60
  37 #define DDR_SDRAM_MODE_2                0x00180000
  38 #define DDR_SDRAM_INTERVAL              0x18600618
  39 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  40 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  41 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  42 #define DDR_DDR_CDR1                    0x80040000
  43 #define DDR_DDR_CDR2                    0x00000001
  44 #define DDR_SDRAM_CLK_CNTL              0x02000000
  45 #define DDR_DDR_ZQ_CNTL                 0x89080600
  46 #define DDR_CS0_CONFIG_2                0
  47 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  48 #define SDRAM_CFG2_D_INIT               0x00000010
  49 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  50 #define SDRAM_CFG2_FRC_SR               0x80000000
  51 #define SDRAM_CFG_BI                    0x00000001
  52
  53 #ifdef CONFIG_SD_BOOT
  54 #ifdef CONFIG_NXP_ESBC
  55 /*
  56  * HDR would be appended at end of image and copied to DDR along
  57  * with U-Boot image.
  58  */
  59 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  60 #endif /* ifdef CONFIG_NXP_ESBC */
  61
  62 #define CONFIG_SPL_MAX_SIZE             0x1a000
  63 #define CONFIG_SPL_STACK                0x1001d000
  64 #define CONFIG_SPL_PAD_TO               0x1c000
  65
  66 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  67                 CONFIG_SYS_MONITOR_LEN)
  68 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  69 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  70 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  71
  72 #ifdef CONFIG_U_BOOT_HDR_SIZE
  73 /*
  74  * HDR would be appended at end of image and copied to DDR along
  75  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  76  * size increases then increase this size in case of secure boot as
  77  * it uses raw u-boot image instead of fit image.
  78  */
  79 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  80 #else
  81 #define CONFIG_SYS_MONITOR_LEN          0x100000
  82 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  83 #endif
  84
  85 #define PHYS_SDRAM                      0x80000000
  86 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  87
  88 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  89 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  90
  91 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  92
  93 /*
  94  * IFC Definitions
  95  */
  96 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  97 #define CONFIG_FSL_IFC
  98 #define CONFIG_SYS_FLASH_BASE           0x60000000
  99 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 100
 101 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 102 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 103                                 CSPR_PORT_SIZE_16 | \
 104                                 CSPR_MSEL_NOR | \
 105                                 CSPR_V)
 106 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 107
 108 /* NOR Flash Timing Params */
 109 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 110                                         CSOR_NOR_TRHZ_80)
 111 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 112                                         FTIM0_NOR_TEADC(0x5) | \
 113                                         FTIM0_NOR_TAVDS(0x0) | \
 114                                         FTIM0_NOR_TEAHC(0x5))
 115 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 116                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 117                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 118 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 119                                         FTIM2_NOR_TCH(0x4) | \
 120                                         FTIM2_NOR_TWP(0x1c) | \
 121                                         FTIM2_NOR_TWPH(0x0e))
 122 #define CONFIG_SYS_NOR_FTIM3            0
 123
 124 #define CONFIG_SYS_FLASH_QUIET_TEST
 125 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 126
 127 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 128 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 129 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 130 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 131
 132 #define CONFIG_SYS_FLASH_EMPTY_INFO
 133 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 134
 135 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 136 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 137 #endif
 138
 139 /* CPLD */
 140
 141 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 142 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 143
 144 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 145 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 146                                         CSPR_PORT_SIZE_8 | \
 147                                         CSPR_MSEL_GPCM | \
 148                                         CSPR_V)
 149 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 150 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 151                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 152                                         CSOR_NOR_TRHZ_80)
 153
 154 /* CPLD Timing parameters for IFC GPCM */
 155 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 156                                         FTIM0_GPCM_TEADC(0xf) | \
 157                                         FTIM0_GPCM_TEAHC(0xf))
 158 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 159                                         FTIM1_GPCM_TRAD(0x3f))
 160 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 161                                         FTIM2_GPCM_TCH(0xf) | \
 162                                         FTIM2_GPCM_TWP(0xff))
 163 #define CONFIG_SYS_FPGA_FTIM3           0x0
 164 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 165 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 166 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 167 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 168 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 169 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 170 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 171 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 172 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 173 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 174 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 175 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 176 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 177 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 178 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 179 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 180
 181 /*
 182  * Serial Port
 183  */
 184 #ifdef CONFIG_LPUART
 185 #define CONFIG_LPUART_32B_REG
 186 #else
 187 #define CONFIG_SYS_NS16550_SERIAL
 188 #ifndef CONFIG_DM_SERIAL
 189 #define CONFIG_SYS_NS16550_REG_SIZE     1
 190 #endif
 191 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 192 #endif
 193
 194 /*
 195  * I2C
 196  */
 197
 198 /* GPIO */
 199 #ifdef CONFIG_DM_GPIO
 200 #ifndef CONFIG_MPC8XXX_GPIO
 201 #define CONFIG_MPC8XXX_GPIO
 202 #endif
 203 #endif
 204
 205 /* EEPROM */
 206 #define CONFIG_SYS_I2C_EEPROM_NXID
 207 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 208
 209 /*
 210  * MMC
 211  */
 212
 213 /*
 214  * Video
 215  */
 216 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 217 #define CONFIG_VIDEO_LOGO
 218 #define CONFIG_VIDEO_BMP_LOGO
 219
 220 #define CONFIG_FSL_DCU_SII9022A
 221 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 222 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 223 #endif
 224
 225 /*
 226  * eTSEC
 227  */
 228
 229 #ifdef CONFIG_TSEC_ENET
 230 #define CONFIG_ETHPRIME                 "ethernet@2d10000"
 231 #endif
 232
 233 /* PCIe */
 234 #define CONFIG_PCIE1            /* PCIE controller 1 */
 235 #define CONFIG_PCIE2            /* PCIE controller 2 */
 236
 237 #ifdef CONFIG_PCI
 238 #define CONFIG_PCI_SCAN_SHOW
 239 #endif
 240
 241 #define CONFIG_CMDLINE_TAG
 242
 243 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 244 #define CONFIG_LAYERSCAPE_NS_ACCESS
 245 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 246 #define COUNTER_FREQUENCY               12500000
 247
 248 #define CONFIG_HWCONFIG
 249 #define HWCONFIG_BUFFER_SIZE            256
 250
 251 #define CONFIG_FSL_DEVICE_DISABLE
 252
 253 #define BOOT_TARGET_DEVICES(func) \
 254         func(MMC, mmc, 0) \
 255         func(USB, usb, 0) \
 256         func(DHCP, dhcp, na)
 257 #include <config_distro_bootcmd.h>
 258
 259 #ifdef CONFIG_LPUART
 260 #define CONFIG_EXTRA_ENV_SETTINGS       \
 261         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 262                 "cma=64M@0x0-0xb0000000\0" \
 263         "initrd_high=0xffffffff\0"      \
 264         "fdt_addr=0x64f00000\0"         \
 265         "kernel_addr=0x65000000\0"      \
 266         "scriptaddr=0x80000000\0"       \
 267         "scripthdraddr=0x80080000\0"    \
 268         "fdtheader_addr_r=0x80100000\0" \
 269         "kernelheader_addr_r=0x80200000\0"      \
 270         "kernel_addr_r=0x81000000\0"    \
 271         "fdt_addr_r=0x90000000\0"       \
 272         "ramdisk_addr_r=0xa0000000\0"   \
 273         "load_addr=0xa0000000\0"        \
 274         "kernel_size=0x2800000\0"       \
 275         "kernel_addr_sd=0x8000\0"       \
 276         "kernel_size_sd=0x14000\0"      \
 277         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 278         BOOTENV                         \
 279         "boot_scripts=ls1021atwr_boot.scr\0"    \
 280         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 281                 "scan_dev_for_boot_part="       \
 282                         "part list ${devtype} ${devnum} devplist; "     \
 283                         "env exists devplist || setenv devplist 1; "    \
 284                         "for distro_bootpart in ${devplist}; do "       \
 285                         "if fstype ${devtype} "                         \
 286                                 "${devnum}:${distro_bootpart} "         \
 287                                 "bootfstype; then "                     \
 288                                 "run scan_dev_for_boot; "               \
 289                         "fi; "                  \
 290                 "done\0"                        \
 291         "scan_dev_for_boot="                              \
 292                 "echo Scanning ${devtype} "               \
 293                                 "${devnum}:${distro_bootpart}...; "  \
 294                 "for prefix in ${boot_prefixes}; do "     \
 295                         "run scan_dev_for_scripts; "      \
 296                 "done;"                                   \
 297                 "\0"                                      \
 298         "boot_a_script="                                  \
 299                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 300                         "${scriptaddr} ${prefix}${script}; "    \
 301                 "env exists secureboot && load ${devtype} "     \
 302                         "${devnum}:${distro_bootpart} "         \
 303                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 304                         "env exists secureboot "        \
 305                         "&& esbc_validate ${scripthdraddr};"    \
 306                 "source ${scriptaddr}\0"          \
 307         "installer=load mmc 0:2 $load_addr "    \
 308                 "/flex_installer_arm32.itb; "           \
 309                 "bootm $load_addr#ls1021atwr\0" \
 310         "qspi_bootcmd=echo Trying load from qspi..;"    \
 311                 "sf probe && sf read $load_addr "       \
 312                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 313         "nor_bootcmd=echo Trying load from nor..;"      \
 314                 "cp.b $kernel_addr $load_addr "         \
 315                 "$kernel_size && bootm $load_addr#$board\0"
 316 #else
 317 #define CONFIG_EXTRA_ENV_SETTINGS       \
 318         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 319                 "cma=64M@0x0-0xb0000000\0" \
 320         "initrd_high=0xffffffff\0"      \
 321         "fdt_addr=0x64f00000\0"         \
 322         "kernel_addr=0x61000000\0"      \
 323         "kernelheader_addr=0x60800000\0"        \
 324         "scriptaddr=0x80000000\0"       \
 325         "scripthdraddr=0x80080000\0"    \
 326         "fdtheader_addr_r=0x80100000\0" \
 327         "kernelheader_addr_r=0x80200000\0"      \
 328         "kernel_addr_r=0x81000000\0"    \
 329         "kernelheader_size=0x40000\0"   \
 330         "fdt_addr_r=0x90000000\0"       \
 331         "ramdisk_addr_r=0xa0000000\0"   \
 332         "load_addr=0xa0000000\0"        \
 333         "kernel_size=0x2800000\0"       \
 334         "kernel_addr_sd=0x8000\0"       \
 335         "kernel_size_sd=0x14000\0"      \
 336         "kernelhdr_addr_sd=0x4000\0"            \
 337         "kernelhdr_size_sd=0x10\0"              \
 338         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 339         BOOTENV                         \
 340         "boot_scripts=ls1021atwr_boot.scr\0"    \
 341         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 342                 "scan_dev_for_boot_part="       \
 343                         "part list ${devtype} ${devnum} devplist; "     \
 344                         "env exists devplist || setenv devplist 1; "    \
 345                         "for distro_bootpart in ${devplist}; do "       \
 346                         "if fstype ${devtype} "                         \
 347                                 "${devnum}:${distro_bootpart} "         \
 348                                 "bootfstype; then "                     \
 349                                 "run scan_dev_for_boot; "               \
 350                         "fi; "                  \
 351                 "done\0"                        \
 352         "scan_dev_for_boot="                              \
 353                 "echo Scanning ${devtype} "               \
 354                                 "${devnum}:${distro_bootpart}...; "  \
 355                 "for prefix in ${boot_prefixes}; do "     \
 356                         "run scan_dev_for_scripts; "      \
 357                 "done;"                                   \
 358                 "\0"                                      \
 359         "boot_a_script="                                  \
 360                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 361                         "${scriptaddr} ${prefix}${script}; "    \
 362                 "env exists secureboot && load ${devtype} "     \
 363                         "${devnum}:${distro_bootpart} "         \
 364                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 365                         "&& esbc_validate ${scripthdraddr};"    \
 366                 "source ${scriptaddr}\0"          \
 367         "qspi_bootcmd=echo Trying load from qspi..;"    \
 368                 "sf probe && sf read $load_addr "       \
 369                 "$kernel_addr $kernel_size; env exists secureboot "     \
 370                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 371                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 372                 "bootm $load_addr#$board\0" \
 373         "nor_bootcmd=echo Trying load from nor..;"      \
 374                 "cp.b $kernel_addr $load_addr "         \
 375                 "$kernel_size; env exists secureboot "  \
 376                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 377                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 378                 "bootm $load_addr#$board\0"     \
 379         "sd_bootcmd=echo Trying load from SD ..;"       \
 380                 "mmcinfo && mmc read $load_addr "       \
 381                 "$kernel_addr_sd $kernel_size_sd && "   \
 382                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 383                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 384                 " && esbc_validate ${kernelheader_addr_r};"     \
 385                 "bootm $load_addr#$board\0"
 386 #endif
 387
 388 #undef CONFIG_BOOTCOMMAND
 389 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 390 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 391                            "env exists secureboot && esbc_halt"
 392 #elif defined(CONFIG_SD_BOOT)
 393 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 394                            "env exists secureboot && esbc_halt;"
 395 #else
 396 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"       \
 397                            "env exists secureboot && esbc_halt;"
 398 #endif
 399
 400 /*
 401  * Miscellaneous configurable options
 402  */
 403 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 404
 405 #define CONFIG_LS102XA_STREAM_ID
 406
 407 #define CONFIG_SYS_INIT_SP_OFFSET \
 408         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 409 #define CONFIG_SYS_INIT_SP_ADDR \
 410         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 411
 412 #ifdef CONFIG_SPL_BUILD
 413 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 414 #else
 415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 416 #endif
 417
 418 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 419
 420 /*
 421  * Environment
 422  */
 423
 424 #include <asm/fsl_secure_boot.h>
 425 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 426
 427 #endif