include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019, 2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #define DDR_SDRAM_CFG                   0x470c0008
  14 #define DDR_CS0_BNDS                    0x008000bf
  15 #define DDR_CS0_CONFIG                  0x80014302
  16 #define DDR_TIMING_CFG_0                0x50550004
  17 #define DDR_TIMING_CFG_1                0xbcb38c56
  18 #define DDR_TIMING_CFG_2                0x0040d120
  19 #define DDR_TIMING_CFG_3                0x010e1000
  20 #define DDR_TIMING_CFG_4                0x00000001
  21 #define DDR_TIMING_CFG_5                0x03401400
  22 #define DDR_SDRAM_CFG_2                 0x00401010
  23 #define DDR_SDRAM_MODE                  0x00061c60
  24 #define DDR_SDRAM_MODE_2                0x00180000
  25 #define DDR_SDRAM_INTERVAL              0x18600618
  26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  29 #define DDR_DDR_CDR1                    0x80040000
  30 #define DDR_DDR_CDR2                    0x00000001
  31 #define DDR_SDRAM_CLK_CNTL              0x02000000
  32 #define DDR_DDR_ZQ_CNTL                 0x89080600
  33 #define DDR_CS0_CONFIG_2                0
  34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  35 #define SDRAM_CFG2_D_INIT               0x00000010
  36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  37 #define SDRAM_CFG2_FRC_SR               0x80000000
  38 #define SDRAM_CFG_BI                    0x00000001
  39
  40 #ifdef CONFIG_SD_BOOT
  41 #ifdef CONFIG_NXP_ESBC
  42 /*
  43  * HDR would be appended at end of image and copied to DDR along
  44  * with U-Boot image.
  45  */
  46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  47 #endif /* ifdef CONFIG_NXP_ESBC */
  48
  49 #define CONFIG_SPL_STACK                0x1001d000
  50
  51 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  52                 CONFIG_SYS_MONITOR_LEN)
  53 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  54 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  55
  56 #ifdef CONFIG_U_BOOT_HDR_SIZE
  57 /*
  58  * HDR would be appended at end of image and copied to DDR along
  59  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  60  * size increases then increase this size in case of secure boot as
  61  * it uses raw u-boot image instead of fit image.
  62  */
  63 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  64 #else
  65 #define CONFIG_SYS_MONITOR_LEN          0x100000
  66 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  67 #endif
  68
  69 #define PHYS_SDRAM                      0x80000000
  70 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  71
  72 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  73 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  74
  75 /*
  76  * IFC Definitions
  77  */
  78 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  79 #define CONFIG_SYS_FLASH_BASE           0x60000000
  80 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  81
  82 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  83 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  84                                 CSPR_PORT_SIZE_16 | \
  85                                 CSPR_MSEL_NOR | \
  86                                 CSPR_V)
  87 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  88
  89 /* NOR Flash Timing Params */
  90 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  91                                         CSOR_NOR_TRHZ_80)
  92 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  93                                         FTIM0_NOR_TEADC(0x5) | \
  94                                         FTIM0_NOR_TAVDS(0x0) | \
  95                                         FTIM0_NOR_TEAHC(0x5))
  96 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  97                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
  98                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  99 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 100                                         FTIM2_NOR_TCH(0x4) | \
 101                                         FTIM2_NOR_TWP(0x1c) | \
 102                                         FTIM2_NOR_TWPH(0x0e))
 103 #define CONFIG_SYS_NOR_FTIM3            0
 104
 105 #define CONFIG_SYS_FLASH_QUIET_TEST
 106 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 107
 108 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 109 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 110 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 111
 112 #define CONFIG_SYS_FLASH_EMPTY_INFO
 113 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 114
 115 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 116 #endif
 117
 118 /* CPLD */
 119
 120 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 121 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 122
 123 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 124 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 125                                         CSPR_PORT_SIZE_8 | \
 126                                         CSPR_MSEL_GPCM | \
 127                                         CSPR_V)
 128 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 129 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 130                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 131                                         CSOR_NOR_TRHZ_80)
 132
 133 /* CPLD Timing parameters for IFC GPCM */
 134 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 135                                         FTIM0_GPCM_TEADC(0xf) | \
 136                                         FTIM0_GPCM_TEAHC(0xf))
 137 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 138                                         FTIM1_GPCM_TRAD(0x3f))
 139 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 140                                         FTIM2_GPCM_TCH(0xf) | \
 141                                         FTIM2_GPCM_TWP(0xff))
 142 #define CONFIG_SYS_FPGA_FTIM3           0x0
 143 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 144 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 145 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 146 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 147 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 148 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 149 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 150 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 151 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 152 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 153 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 154 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 155 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 156 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 157 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 158 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 159
 160 /*
 161  * Serial Port
 162  */
 163 #ifndef CONFIG_LPUART
 164 #define CONFIG_SYS_NS16550_SERIAL
 165 #ifndef CONFIG_DM_SERIAL
 166 #define CONFIG_SYS_NS16550_REG_SIZE     1
 167 #endif
 168 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 169 #endif
 170
 171 /*
 172  * I2C
 173  */
 174
 175 /* GPIO */
 176
 177 /* EEPROM */
 178 #define CONFIG_SYS_I2C_EEPROM_NXID
 179 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 180
 181 /* PCIe */
 182 #define CONFIG_PCIE1            /* PCIE controller 1 */
 183 #define CONFIG_PCIE2            /* PCIE controller 2 */
 184
 185 #ifdef CONFIG_PCI
 186 #define CONFIG_PCI_SCAN_SHOW
 187 #endif
 188
 189 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 190 #define CONFIG_LAYERSCAPE_NS_ACCESS
 191 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 192
 193 #define CONFIG_HWCONFIG
 194 #define HWCONFIG_BUFFER_SIZE            256
 195
 196 #define CONFIG_FSL_DEVICE_DISABLE
 197
 198 #define BOOT_TARGET_DEVICES(func) \
 199         func(MMC, mmc, 0) \
 200         func(USB, usb, 0) \
 201         func(DHCP, dhcp, na)
 202 #include <config_distro_bootcmd.h>
 203
 204 #ifdef CONFIG_LPUART
 205 #define CONFIG_EXTRA_ENV_SETTINGS       \
 206         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 207                 "cma=64M@0x0-0xb0000000\0" \
 208         "initrd_high=0xffffffff\0"      \
 209         "kernel_addr=0x65000000\0"      \
 210         "scriptaddr=0x80000000\0"       \
 211         "scripthdraddr=0x80080000\0"    \
 212         "fdtheader_addr_r=0x80100000\0" \
 213         "kernelheader_addr_r=0x80200000\0"      \
 214         "kernel_addr_r=0x81000000\0"    \
 215         "fdt_addr_r=0x90000000\0"       \
 216         "ramdisk_addr_r=0xa0000000\0"   \
 217         "load_addr=0xa0000000\0"        \
 218         "kernel_size=0x2800000\0"       \
 219         "kernel_addr_sd=0x8000\0"       \
 220         "kernel_size_sd=0x14000\0"      \
 221         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 222         BOOTENV                         \
 223         "boot_scripts=ls1021atwr_boot.scr\0"    \
 224         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 225                 "scan_dev_for_boot_part="       \
 226                         "part list ${devtype} ${devnum} devplist; "     \
 227                         "env exists devplist || setenv devplist 1; "    \
 228                         "for distro_bootpart in ${devplist}; do "       \
 229                         "if fstype ${devtype} "                         \
 230                                 "${devnum}:${distro_bootpart} "         \
 231                                 "bootfstype; then "                     \
 232                                 "run scan_dev_for_boot; "               \
 233                         "fi; "                  \
 234                 "done\0"                        \
 235         "scan_dev_for_boot="                              \
 236                 "echo Scanning ${devtype} "               \
 237                                 "${devnum}:${distro_bootpart}...; "  \
 238                 "for prefix in ${boot_prefixes}; do "     \
 239                         "run scan_dev_for_scripts; "      \
 240                 "done;"                                   \
 241                 "\0"                                      \
 242         "boot_a_script="                                  \
 243                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 244                         "${scriptaddr} ${prefix}${script}; "    \
 245                 "env exists secureboot && load ${devtype} "     \
 246                         "${devnum}:${distro_bootpart} "         \
 247                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 248                         "env exists secureboot "        \
 249                         "&& esbc_validate ${scripthdraddr};"    \
 250                 "source ${scriptaddr}\0"          \
 251         "installer=load mmc 0:2 $load_addr "    \
 252                 "/flex_installer_arm32.itb; "           \
 253                 "bootm $load_addr#ls1021atwr\0" \
 254         "qspi_bootcmd=echo Trying load from qspi..;"    \
 255                 "sf probe && sf read $load_addr "       \
 256                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 257         "nor_bootcmd=echo Trying load from nor..;"      \
 258                 "cp.b $kernel_addr $load_addr "         \
 259                 "$kernel_size && bootm $load_addr#$board\0"
 260 #else
 261 #define CONFIG_EXTRA_ENV_SETTINGS       \
 262         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 263                 "cma=64M@0x0-0xb0000000\0" \
 264         "initrd_high=0xffffffff\0"      \
 265         "kernel_addr=0x61000000\0"      \
 266         "kernelheader_addr=0x60800000\0"        \
 267         "scriptaddr=0x80000000\0"       \
 268         "scripthdraddr=0x80080000\0"    \
 269         "fdtheader_addr_r=0x80100000\0" \
 270         "kernelheader_addr_r=0x80200000\0"      \
 271         "kernel_addr_r=0x81000000\0"    \
 272         "kernelheader_size=0x40000\0"   \
 273         "fdt_addr_r=0x90000000\0"       \
 274         "ramdisk_addr_r=0xa0000000\0"   \
 275         "load_addr=0xa0000000\0"        \
 276         "kernel_size=0x2800000\0"       \
 277         "kernel_addr_sd=0x8000\0"       \
 278         "kernel_size_sd=0x14000\0"      \
 279         "kernelhdr_addr_sd=0x4000\0"            \
 280         "kernelhdr_size_sd=0x10\0"              \
 281         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 282         BOOTENV                         \
 283         "boot_scripts=ls1021atwr_boot.scr\0"    \
 284         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 285                 "scan_dev_for_boot_part="       \
 286                         "part list ${devtype} ${devnum} devplist; "     \
 287                         "env exists devplist || setenv devplist 1; "    \
 288                         "for distro_bootpart in ${devplist}; do "       \
 289                         "if fstype ${devtype} "                         \
 290                                 "${devnum}:${distro_bootpart} "         \
 291                                 "bootfstype; then "                     \
 292                                 "run scan_dev_for_boot; "               \
 293                         "fi; "                  \
 294                 "done\0"                        \
 295         "scan_dev_for_boot="                              \
 296                 "echo Scanning ${devtype} "               \
 297                                 "${devnum}:${distro_bootpart}...; "  \
 298                 "for prefix in ${boot_prefixes}; do "     \
 299                         "run scan_dev_for_scripts; "      \
 300                 "done;"                                   \
 301                 "\0"                                      \
 302         "boot_a_script="                                  \
 303                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 304                         "${scriptaddr} ${prefix}${script}; "    \
 305                 "env exists secureboot && load ${devtype} "     \
 306                         "${devnum}:${distro_bootpart} "         \
 307                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 308                         "&& esbc_validate ${scripthdraddr};"    \
 309                 "source ${scriptaddr}\0"          \
 310         "qspi_bootcmd=echo Trying load from qspi..;"    \
 311                 "sf probe && sf read $load_addr "       \
 312                 "$kernel_addr $kernel_size; env exists secureboot "     \
 313                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 314                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 315                 "bootm $load_addr#$board\0" \
 316         "nor_bootcmd=echo Trying load from nor..;"      \
 317                 "cp.b $kernel_addr $load_addr "         \
 318                 "$kernel_size; env exists secureboot "  \
 319                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 320                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 321                 "bootm $load_addr#$board\0"     \
 322         "sd_bootcmd=echo Trying load from SD ..;"       \
 323                 "mmcinfo && mmc read $load_addr "       \
 324                 "$kernel_addr_sd $kernel_size_sd && "   \
 325                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 326                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 327                 " && esbc_validate ${kernelheader_addr_r};"     \
 328                 "bootm $load_addr#$board\0"
 329 #endif
 330
 331 /*
 332  * Miscellaneous configurable options
 333  */
 334 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 335
 336 #define CONFIG_LS102XA_STREAM_ID
 337
 338 #define CONFIG_SYS_INIT_SP_OFFSET \
 339         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 340 #define CONFIG_SYS_INIT_SP_ADDR \
 341         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 342
 343 /*
 344  * Environment
 345  */
 346
 347 #include <asm/fsl_secure_boot.h>
 348 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 349
 350 #endif