1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2019, 2021 NXP
10 #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11 #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
13 #define DDR_SDRAM_CFG 0x470c0008
14 #define DDR_CS0_BNDS 0x008000bf
15 #define DDR_CS0_CONFIG 0x80014302
16 #define DDR_TIMING_CFG_0 0x50550004
17 #define DDR_TIMING_CFG_1 0xbcb38c56
18 #define DDR_TIMING_CFG_2 0x0040d120
19 #define DDR_TIMING_CFG_3 0x010e1000
20 #define DDR_TIMING_CFG_4 0x00000001
21 #define DDR_TIMING_CFG_5 0x03401400
22 #define DDR_SDRAM_CFG_2 0x00401010
23 #define DDR_SDRAM_MODE 0x00061c60
24 #define DDR_SDRAM_MODE_2 0x00180000
25 #define DDR_SDRAM_INTERVAL 0x18600618
26 #define DDR_DDR_WRLVL_CNTL 0x8655f605
27 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
28 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
29 #define DDR_DDR_CDR1 0x80040000
30 #define DDR_DDR_CDR2 0x00000001
31 #define DDR_SDRAM_CLK_CNTL 0x02000000
32 #define DDR_DDR_ZQ_CNTL 0x89080600
33 #define DDR_CS0_CONFIG_2 0
34 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
35 #define SDRAM_CFG2_D_INIT 0x00000010
36 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
37 #define SDRAM_CFG2_FRC_SR 0x80000000
38 #define SDRAM_CFG_BI 0x00000001
41 #ifdef CONFIG_NXP_ESBC
43 * HDR would be appended at end of image and copied to DDR along
46 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
47 #endif /* ifdef CONFIG_NXP_ESBC */
49 #ifdef CONFIG_U_BOOT_HDR_SIZE
51 * HDR would be appended at end of image and copied to DDR along
52 * with U-Boot image. Here u-boot max. size is 512K. So if binary
53 * size increases then increase this size in case of secure boot as
54 * it uses raw u-boot image instead of fit image.
56 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
59 #define PHYS_SDRAM 0x80000000
60 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
62 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
63 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
68 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
69 #define CFG_SYS_FLASH_BASE 0x60000000
70 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
72 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
73 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
77 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
79 /* NOR Flash Timing Params */
80 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
82 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
83 FTIM0_NOR_TEADC(0x5) | \
84 FTIM0_NOR_TAVDS(0x0) | \
86 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
87 FTIM1_NOR_TRAD_NOR(0x1A) | \
88 FTIM1_NOR_TSEQRAD_NOR(0x13))
89 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
90 FTIM2_NOR_TCH(0x4) | \
91 FTIM2_NOR_TWP(0x1c) | \
93 #define CFG_SYS_NOR_FTIM3 0
95 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
97 #define CFG_SYS_WRITE_SWAPPED_DATA
102 #define CFG_SYS_CPLD_BASE 0x7fb00000
103 #define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
105 #define CFG_SYS_FPGA_CSPR_EXT (0x0)
106 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
110 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
111 #define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
112 CSOR_NOR_NOR_MODE_AVD_NOR | \
115 /* CPLD Timing parameters for IFC GPCM */
116 #define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
117 FTIM0_GPCM_TEADC(0xf) | \
118 FTIM0_GPCM_TEAHC(0xf))
119 #define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
120 FTIM1_GPCM_TRAD(0x3f))
121 #define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
122 FTIM2_GPCM_TCH(0xf) | \
123 FTIM2_GPCM_TWP(0xff))
124 #define CFG_SYS_FPGA_FTIM3 0x0
125 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
126 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
127 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
128 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
129 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
130 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
131 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
132 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
133 #define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT
134 #define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR
135 #define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK
136 #define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR
137 #define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0
138 #define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1
139 #define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2
140 #define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
145 #ifndef CONFIG_LPUART
146 #define CFG_SYS_NS16550_CLK get_serial_clock()
155 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
157 #define HWCONFIG_BUFFER_SIZE 256
159 #define BOOT_TARGET_DEVICES(func) \
163 #include <config_distro_bootcmd.h>
166 #define CONFIG_EXTRA_ENV_SETTINGS \
167 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
168 "cma=64M@0x0-0xb0000000\0" \
169 "initrd_high=0xffffffff\0" \
170 "kernel_addr=0x65000000\0" \
171 "scriptaddr=0x80000000\0" \
172 "scripthdraddr=0x80080000\0" \
173 "fdtheader_addr_r=0x80100000\0" \
174 "kernelheader_addr_r=0x80200000\0" \
175 "kernel_addr_r=0x81000000\0" \
176 "fdt_addr_r=0x90000000\0" \
177 "ramdisk_addr_r=0xa0000000\0" \
178 "load_addr=0xa0000000\0" \
179 "kernel_size=0x2800000\0" \
180 "kernel_addr_sd=0x8000\0" \
181 "kernel_size_sd=0x14000\0" \
182 "othbootargs=cma=64M@0x0-0xb0000000\0" \
184 "boot_scripts=ls1021atwr_boot.scr\0" \
185 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
186 "scan_dev_for_boot_part=" \
187 "part list ${devtype} ${devnum} devplist; " \
188 "env exists devplist || setenv devplist 1; " \
189 "for distro_bootpart in ${devplist}; do " \
190 "if fstype ${devtype} " \
191 "${devnum}:${distro_bootpart} " \
192 "bootfstype; then " \
193 "run scan_dev_for_boot; " \
196 "scan_dev_for_boot=" \
197 "echo Scanning ${devtype} " \
198 "${devnum}:${distro_bootpart}...; " \
199 "for prefix in ${boot_prefixes}; do " \
200 "run scan_dev_for_scripts; " \
204 "load ${devtype} ${devnum}:${distro_bootpart} " \
205 "${scriptaddr} ${prefix}${script}; " \
206 "env exists secureboot && load ${devtype} " \
207 "${devnum}:${distro_bootpart} " \
208 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
209 "env exists secureboot " \
210 "&& esbc_validate ${scripthdraddr};" \
211 "source ${scriptaddr}\0" \
212 "installer=load mmc 0:2 $load_addr " \
213 "/flex_installer_arm32.itb; " \
214 "bootm $load_addr#ls1021atwr\0" \
215 "qspi_bootcmd=echo Trying load from qspi..;" \
216 "sf probe && sf read $load_addr " \
217 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
218 "nor_bootcmd=echo Trying load from nor..;" \
219 "cp.b $kernel_addr $load_addr " \
220 "$kernel_size && bootm $load_addr#$board\0"
222 #define CONFIG_EXTRA_ENV_SETTINGS \
223 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
224 "cma=64M@0x0-0xb0000000\0" \
225 "initrd_high=0xffffffff\0" \
226 "kernel_addr=0x61000000\0" \
227 "kernelheader_addr=0x60800000\0" \
228 "scriptaddr=0x80000000\0" \
229 "scripthdraddr=0x80080000\0" \
230 "fdtheader_addr_r=0x80100000\0" \
231 "kernelheader_addr_r=0x80200000\0" \
232 "kernel_addr_r=0x81000000\0" \
233 "kernelheader_size=0x40000\0" \
234 "fdt_addr_r=0x90000000\0" \
235 "ramdisk_addr_r=0xa0000000\0" \
236 "load_addr=0xa0000000\0" \
237 "kernel_size=0x2800000\0" \
238 "kernel_addr_sd=0x8000\0" \
239 "kernel_size_sd=0x14000\0" \
240 "kernelhdr_addr_sd=0x4000\0" \
241 "kernelhdr_size_sd=0x10\0" \
242 "othbootargs=cma=64M@0x0-0xb0000000\0" \
244 "boot_scripts=ls1021atwr_boot.scr\0" \
245 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
246 "scan_dev_for_boot_part=" \
247 "part list ${devtype} ${devnum} devplist; " \
248 "env exists devplist || setenv devplist 1; " \
249 "for distro_bootpart in ${devplist}; do " \
250 "if fstype ${devtype} " \
251 "${devnum}:${distro_bootpart} " \
252 "bootfstype; then " \
253 "run scan_dev_for_boot; " \
256 "scan_dev_for_boot=" \
257 "echo Scanning ${devtype} " \
258 "${devnum}:${distro_bootpart}...; " \
259 "for prefix in ${boot_prefixes}; do " \
260 "run scan_dev_for_scripts; " \
264 "load ${devtype} ${devnum}:${distro_bootpart} " \
265 "${scriptaddr} ${prefix}${script}; " \
266 "env exists secureboot && load ${devtype} " \
267 "${devnum}:${distro_bootpart} " \
268 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
269 "&& esbc_validate ${scripthdraddr};" \
270 "source ${scriptaddr}\0" \
271 "qspi_bootcmd=echo Trying load from qspi..;" \
272 "sf probe && sf read $load_addr " \
273 "$kernel_addr $kernel_size; env exists secureboot " \
274 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
275 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
276 "bootm $load_addr#$board\0" \
277 "nor_bootcmd=echo Trying load from nor..;" \
278 "cp.b $kernel_addr $load_addr " \
279 "$kernel_size; env exists secureboot " \
280 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
281 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
282 "bootm $load_addr#$board\0" \
283 "sd_bootcmd=echo Trying load from SD ..;" \
284 "mmcinfo && mmc read $load_addr " \
285 "$kernel_addr_sd $kernel_size_sd && " \
286 "env exists secureboot && mmc read $kernelheader_addr_r " \
287 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
288 " && esbc_validate ${kernelheader_addr_r};" \
289 "bootm $load_addr#$board\0"
293 * Miscellaneous configurable options
295 #define CFG_SYS_BOOTMAPSZ (256 << 20)
301 #include <asm/fsl_secure_boot.h>