Merge git://git.denx.de/u-boot-nand-flash
[platform/kernel/u-boot.git] / include / configs / ls1021atwr.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_LS102XA
11
12 #define CONFIG_ARMV7_PSCI
13
14 #define CONFIG_SYS_FSL_CLK
15
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21 #define CONFIG_DEEP_SLEEP
22 #ifdef CONFIG_DEEP_SLEEP
23 #define CONFIG_SILENT_CONSOLE
24 #endif
25
26 /*
27  * Size of malloc() pool
28  */
29 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30
31 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
32 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
33
34 /*
35  * USB
36  */
37
38 /*
39  * EHCI Support - disbaled by default as
40  * there is no signal coming out of soc on
41  * this board for this controller. However,
42  * the silicon still has this controller,
43  * and anyone can use this controller by
44  * taking signals out on their board.
45  */
46
47 /*#define CONFIG_HAS_FSL_DR_USB*/
48
49 #ifdef CONFIG_HAS_FSL_DR_USB
50 #define CONFIG_USB_EHCI
51 #define CONFIG_USB_EHCI_FSL
52 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
53 #endif
54
55 /* XHCI Support - enabled by default */
56 #define CONFIG_HAS_FSL_XHCI_USB
57
58 #ifdef CONFIG_HAS_FSL_XHCI_USB
59 #define CONFIG_USB_XHCI_FSL
60 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
61 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
62 #endif
63
64 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
65 #define CONFIG_USB_STORAGE
66 #endif
67
68 /*
69  * Generic Timer Definitions
70  */
71 #define GENERIC_TIMER_CLK               12500000
72
73 #define CONFIG_SYS_CLK_FREQ             100000000
74 #define CONFIG_DDR_CLK_FREQ             100000000
75
76 #define DDR_SDRAM_CFG                   0x470c0008
77 #define DDR_CS0_BNDS                    0x008000bf
78 #define DDR_CS0_CONFIG                  0x80014302
79 #define DDR_TIMING_CFG_0                0x50550004
80 #define DDR_TIMING_CFG_1                0xbcb38c56
81 #define DDR_TIMING_CFG_2                0x0040d120
82 #define DDR_TIMING_CFG_3                0x010e1000
83 #define DDR_TIMING_CFG_4                0x00000001
84 #define DDR_TIMING_CFG_5                0x03401400
85 #define DDR_SDRAM_CFG_2                 0x00401010
86 #define DDR_SDRAM_MODE                  0x00061c60
87 #define DDR_SDRAM_MODE_2                0x00180000
88 #define DDR_SDRAM_INTERVAL              0x18600618
89 #define DDR_DDR_WRLVL_CNTL              0x8655f605
90 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
91 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
92 #define DDR_DDR_CDR1                    0x80040000
93 #define DDR_DDR_CDR2                    0x00000001
94 #define DDR_SDRAM_CLK_CNTL              0x02000000
95 #define DDR_DDR_ZQ_CNTL                 0x89080600
96 #define DDR_CS0_CONFIG_2                0
97 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
98 #define SDRAM_CFG2_D_INIT               0x00000010
99 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
100 #define SDRAM_CFG2_FRC_SR               0x80000000
101 #define SDRAM_CFG_BI                    0x00000001
102
103 #ifdef CONFIG_RAMBOOT_PBL
104 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
105 #endif
106
107 #ifdef CONFIG_SD_BOOT
108 #ifdef CONFIG_SD_BOOT_QSPI
109 #define CONFIG_SYS_FSL_PBL_RCW  \
110         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
111 #else
112 #define CONFIG_SYS_FSL_PBL_RCW  \
113         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
114 #endif
115 #define CONFIG_SPL_FRAMEWORK
116 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
117 #define CONFIG_SPL_LIBCOMMON_SUPPORT
118 #define CONFIG_SPL_LIBGENERIC_SUPPORT
119 #define CONFIG_SPL_ENV_SUPPORT
120 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
121 #define CONFIG_SPL_I2C_SUPPORT
122 #define CONFIG_SPL_WATCHDOG_SUPPORT
123 #define CONFIG_SPL_SERIAL_SUPPORT
124 #define CONFIG_SPL_MMC_SUPPORT
125 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
126 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
127
128 #define CONFIG_SPL_TEXT_BASE            0x10000000
129 #define CONFIG_SPL_MAX_SIZE             0x1a000
130 #define CONFIG_SPL_STACK                0x1001d000
131 #define CONFIG_SPL_PAD_TO               0x1c000
132 #define CONFIG_SYS_TEXT_BASE            0x82000000
133
134 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
135                 CONFIG_SYS_MONITOR_LEN)
136 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
137 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
138 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
139 #define CONFIG_SYS_MONITOR_LEN          0x80000
140 #endif
141
142 #ifdef CONFIG_QSPI_BOOT
143 #define CONFIG_SYS_TEXT_BASE            0x40010000
144 #endif
145
146 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
147 #define CONFIG_SYS_NO_FLASH
148 #endif
149
150 #ifndef CONFIG_SYS_TEXT_BASE
151 #define CONFIG_SYS_TEXT_BASE            0x60100000
152 #endif
153
154 #define CONFIG_NR_DRAM_BANKS            1
155 #define PHYS_SDRAM                      0x80000000
156 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
157
158 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
159 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
160
161 #define CONFIG_SYS_HAS_SERDES
162
163 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
164
165 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
166         !defined(CONFIG_QSPI_BOOT)
167 #define CONFIG_U_QE
168 #endif
169
170 /*
171  * IFC Definitions
172  */
173 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
174 #define CONFIG_FSL_IFC
175 #define CONFIG_SYS_FLASH_BASE           0x60000000
176 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
177
178 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
179 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
180                                 CSPR_PORT_SIZE_16 | \
181                                 CSPR_MSEL_NOR | \
182                                 CSPR_V)
183 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
184
185 /* NOR Flash Timing Params */
186 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
187                                         CSOR_NOR_TRHZ_80)
188 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
189                                         FTIM0_NOR_TEADC(0x5) | \
190                                         FTIM0_NOR_TAVDS(0x0) | \
191                                         FTIM0_NOR_TEAHC(0x5))
192 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
193                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
194                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
195 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
196                                         FTIM2_NOR_TCH(0x4) | \
197                                         FTIM2_NOR_TWP(0x1c) | \
198                                         FTIM2_NOR_TWPH(0x0e))
199 #define CONFIG_SYS_NOR_FTIM3            0
200
201 #define CONFIG_FLASH_CFI_DRIVER
202 #define CONFIG_SYS_FLASH_CFI
203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
204 #define CONFIG_SYS_FLASH_QUIET_TEST
205 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
206
207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
208 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
209 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
211
212 #define CONFIG_SYS_FLASH_EMPTY_INFO
213 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
214
215 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
216 #define CONFIG_SYS_WRITE_SWAPPED_DATA
217 #endif
218
219 /* CPLD */
220
221 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
222 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
223
224 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
225 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
226                                         CSPR_PORT_SIZE_8 | \
227                                         CSPR_MSEL_GPCM | \
228                                         CSPR_V)
229 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
230 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
231                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
232                                         CSOR_NOR_TRHZ_80)
233
234 /* CPLD Timing parameters for IFC GPCM */
235 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
236                                         FTIM0_GPCM_TEADC(0xf) | \
237                                         FTIM0_GPCM_TEAHC(0xf))
238 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
239                                         FTIM1_GPCM_TRAD(0x3f))
240 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
241                                         FTIM2_GPCM_TCH(0xf) | \
242                                         FTIM2_GPCM_TWP(0xff))
243 #define CONFIG_SYS_FPGA_FTIM3           0x0
244 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
245 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
246 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
247 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
248 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
249 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
250 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
251 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
252 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
253 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
255 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
256 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
260
261 /*
262  * Serial Port
263  */
264 #ifdef CONFIG_LPUART
265 #define CONFIG_LPUART_32B_REG
266 #else
267 #define CONFIG_CONS_INDEX               1
268 #define CONFIG_SYS_NS16550_SERIAL
269 #ifndef CONFIG_DM_SERIAL
270 #define CONFIG_SYS_NS16550_REG_SIZE     1
271 #endif
272 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
273 #endif
274
275 #define CONFIG_BAUDRATE                 115200
276
277 /*
278  * I2C
279  */
280 #define CONFIG_SYS_I2C
281 #define CONFIG_SYS_I2C_MXC
282 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
283 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
284 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
285
286 /* EEPROM */
287 #define CONFIG_ID_EEPROM
288 #define CONFIG_SYS_I2C_EEPROM_NXID
289 #define CONFIG_SYS_EEPROM_BUS_NUM               1
290 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
291 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
292 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
293 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
294
295 /*
296  * MMC
297  */
298 #define CONFIG_MMC
299 #define CONFIG_FSL_ESDHC
300 #define CONFIG_GENERIC_MMC
301
302 #define CONFIG_DOS_PARTITION
303
304 /* SPI */
305 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
306 /* QSPI */
307 #define QSPI0_AMBA_BASE                 0x40000000
308 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
309 #define FSL_QSPI_FLASH_NUM              2
310
311 /* DSPI */
312 #endif
313
314 /* DM SPI */
315 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
316 #define CONFIG_DM_SPI_FLASH
317 #endif
318
319 /*
320  * Video
321  */
322 #define CONFIG_FSL_DCU_FB
323
324 #ifdef CONFIG_FSL_DCU_FB
325 #define CONFIG_VIDEO
326 #define CONFIG_CMD_BMP
327 #define CONFIG_CFB_CONSOLE
328 #define CONFIG_VGA_AS_SINGLE_DEVICE
329 #define CONFIG_VIDEO_LOGO
330 #define CONFIG_VIDEO_BMP_LOGO
331 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
332
333 #define CONFIG_FSL_DCU_SII9022A
334 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
335 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
336 #endif
337
338 /*
339  * eTSEC
340  */
341 #define CONFIG_TSEC_ENET
342
343 #ifdef CONFIG_TSEC_ENET
344 #define CONFIG_MII
345 #define CONFIG_MII_DEFAULT_TSEC         1
346 #define CONFIG_TSEC1                    1
347 #define CONFIG_TSEC1_NAME               "eTSEC1"
348 #define CONFIG_TSEC2                    1
349 #define CONFIG_TSEC2_NAME               "eTSEC2"
350 #define CONFIG_TSEC3                    1
351 #define CONFIG_TSEC3_NAME               "eTSEC3"
352
353 #define TSEC1_PHY_ADDR                  2
354 #define TSEC2_PHY_ADDR                  0
355 #define TSEC3_PHY_ADDR                  1
356
357 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
358 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
359 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
360
361 #define TSEC1_PHYIDX                    0
362 #define TSEC2_PHYIDX                    0
363 #define TSEC3_PHYIDX                    0
364
365 #define CONFIG_ETHPRIME                 "eTSEC1"
366
367 #define CONFIG_PHY_GIGE
368 #define CONFIG_PHYLIB
369 #define CONFIG_PHY_ATHEROS
370
371 #define CONFIG_HAS_ETH0
372 #define CONFIG_HAS_ETH1
373 #define CONFIG_HAS_ETH2
374 #endif
375
376 /* PCIe */
377 #define CONFIG_PCI              /* Enable PCI/PCIE */
378 #define CONFIG_PCIE1            /* PCIE controller 1 */
379 #define CONFIG_PCIE2            /* PCIE controller 2 */
380 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
381 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
382
383 #define CONFIG_SYS_PCI_64BIT
384
385 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
386 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
387 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
388 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
389
390 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
391 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
392 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
393
394 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
395 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
396 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
397
398 #ifdef CONFIG_PCI
399 #define CONFIG_PCI_PNP
400 #define CONFIG_PCI_SCAN_SHOW
401 #define CONFIG_CMD_PCI
402 #endif
403
404 #define CONFIG_CMDLINE_TAG
405 #define CONFIG_CMDLINE_EDITING
406
407 #define CONFIG_ARMV7_NONSEC
408 #define CONFIG_ARMV7_VIRT
409 #define CONFIG_PEN_ADDR_BIG_ENDIAN
410 #define CONFIG_LAYERSCAPE_NS_ACCESS
411 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
412 #define CONFIG_TIMER_CLK_FREQ           12500000
413
414 #define CONFIG_HWCONFIG
415 #define HWCONFIG_BUFFER_SIZE            256
416
417 #define CONFIG_FSL_DEVICE_DISABLE
418
419
420 #ifdef CONFIG_LPUART
421 #define CONFIG_EXTRA_ENV_SETTINGS       \
422         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
423         "initrd_high=0xffffffff\0"      \
424         "fdt_high=0xffffffff\0"
425 #else
426 #define CONFIG_EXTRA_ENV_SETTINGS       \
427         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
428         "initrd_high=0xffffffff\0"      \
429         "fdt_high=0xffffffff\0"
430 #endif
431
432 /*
433  * Miscellaneous configurable options
434  */
435 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
436 #define CONFIG_AUTO_COMPLETE
437 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
438 #define CONFIG_SYS_PBSIZE               \
439                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
440 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
441 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
442
443 #define CONFIG_SYS_MEMTEST_START        0x80000000
444 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
445
446 #define CONFIG_SYS_LOAD_ADDR            0x82000000
447
448 #define CONFIG_LS102XA_STREAM_ID
449
450 /*
451  * Stack sizes
452  * The stack sizes are set up in start.S using the settings below
453  */
454 #define CONFIG_STACKSIZE                (30 * 1024)
455
456 #define CONFIG_SYS_INIT_SP_OFFSET \
457         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
458 #define CONFIG_SYS_INIT_SP_ADDR \
459         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
460
461 #ifdef CONFIG_SPL_BUILD
462 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
463 #else
464 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
465 #endif
466
467 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
468
469 /*
470  * Environment
471  */
472 #define CONFIG_ENV_OVERWRITE
473
474 #if defined(CONFIG_SD_BOOT)
475 #define CONFIG_ENV_OFFSET               0x100000
476 #define CONFIG_ENV_IS_IN_MMC
477 #define CONFIG_SYS_MMC_ENV_DEV          0
478 #define CONFIG_ENV_SIZE                 0x20000
479 #elif defined(CONFIG_QSPI_BOOT)
480 #define CONFIG_ENV_IS_IN_SPI_FLASH
481 #define CONFIG_ENV_SIZE                 0x2000
482 #define CONFIG_ENV_OFFSET               0x100000
483 #define CONFIG_ENV_SECT_SIZE            0x10000
484 #else
485 #define CONFIG_ENV_IS_IN_FLASH
486 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
487 #define CONFIG_ENV_SIZE                 0x20000
488 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
489 #endif
490
491 #define CONFIG_MISC_INIT_R
492
493 /* Hash command with SHA acceleration supported in hardware */
494 #ifdef CONFIG_FSL_CAAM
495 #define CONFIG_CMD_HASH
496 #define CONFIG_SHA_HW_ACCEL
497 #endif
498
499 #include <asm/fsl_secure_boot.h>
500 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
501
502 #endif