Merge branch '2021-12-27-CONFIG-migrations' into next
[platform/kernel/u-boot.git] / include / configs / ls1021atwr.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2019 NXP
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
11
12 #define CONFIG_DEEP_SLEEP
13
14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
16
17 #define DDR_SDRAM_CFG                   0x470c0008
18 #define DDR_CS0_BNDS                    0x008000bf
19 #define DDR_CS0_CONFIG                  0x80014302
20 #define DDR_TIMING_CFG_0                0x50550004
21 #define DDR_TIMING_CFG_1                0xbcb38c56
22 #define DDR_TIMING_CFG_2                0x0040d120
23 #define DDR_TIMING_CFG_3                0x010e1000
24 #define DDR_TIMING_CFG_4                0x00000001
25 #define DDR_TIMING_CFG_5                0x03401400
26 #define DDR_SDRAM_CFG_2                 0x00401010
27 #define DDR_SDRAM_MODE                  0x00061c60
28 #define DDR_SDRAM_MODE_2                0x00180000
29 #define DDR_SDRAM_INTERVAL              0x18600618
30 #define DDR_DDR_WRLVL_CNTL              0x8655f605
31 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
32 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
33 #define DDR_DDR_CDR1                    0x80040000
34 #define DDR_DDR_CDR2                    0x00000001
35 #define DDR_SDRAM_CLK_CNTL              0x02000000
36 #define DDR_DDR_ZQ_CNTL                 0x89080600
37 #define DDR_CS0_CONFIG_2                0
38 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
39 #define SDRAM_CFG2_D_INIT               0x00000010
40 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
41 #define SDRAM_CFG2_FRC_SR               0x80000000
42 #define SDRAM_CFG_BI                    0x00000001
43
44 #ifdef CONFIG_SD_BOOT
45 #ifdef CONFIG_NXP_ESBC
46 /*
47  * HDR would be appended at end of image and copied to DDR along
48  * with U-Boot image.
49  */
50 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
51 #endif /* ifdef CONFIG_NXP_ESBC */
52
53 #define CONFIG_SPL_MAX_SIZE             0x1a000
54 #define CONFIG_SPL_STACK                0x1001d000
55 #define CONFIG_SPL_PAD_TO               0x1c000
56
57 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
58                 CONFIG_SYS_MONITOR_LEN)
59 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
60 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
61 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
62
63 #ifdef CONFIG_U_BOOT_HDR_SIZE
64 /*
65  * HDR would be appended at end of image and copied to DDR along
66  * with U-Boot image. Here u-boot max. size is 512K. So if binary
67  * size increases then increase this size in case of secure boot as
68  * it uses raw u-boot image instead of fit image.
69  */
70 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
71 #else
72 #define CONFIG_SYS_MONITOR_LEN          0x100000
73 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
74 #endif
75
76 #define PHYS_SDRAM                      0x80000000
77 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
78
79 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
80 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
81
82 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
83
84 /*
85  * IFC Definitions
86  */
87 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
88 #define CONFIG_SYS_FLASH_BASE           0x60000000
89 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
90
91 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
92 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
93                                 CSPR_PORT_SIZE_16 | \
94                                 CSPR_MSEL_NOR | \
95                                 CSPR_V)
96 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
97
98 /* NOR Flash Timing Params */
99 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
100                                         CSOR_NOR_TRHZ_80)
101 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
102                                         FTIM0_NOR_TEADC(0x5) | \
103                                         FTIM0_NOR_TAVDS(0x0) | \
104                                         FTIM0_NOR_TEAHC(0x5))
105 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
106                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
107                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
108 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
109                                         FTIM2_NOR_TCH(0x4) | \
110                                         FTIM2_NOR_TWP(0x1c) | \
111                                         FTIM2_NOR_TWPH(0x0e))
112 #define CONFIG_SYS_NOR_FTIM3            0
113
114 #define CONFIG_SYS_FLASH_QUIET_TEST
115 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
116
117 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
118 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
119 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
121
122 #define CONFIG_SYS_FLASH_EMPTY_INFO
123 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
124
125 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
126 #define CONFIG_SYS_WRITE_SWAPPED_DATA
127 #endif
128
129 /* CPLD */
130
131 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
132 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
133
134 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
135 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
136                                         CSPR_PORT_SIZE_8 | \
137                                         CSPR_MSEL_GPCM | \
138                                         CSPR_V)
139 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
140 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
141                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
142                                         CSOR_NOR_TRHZ_80)
143
144 /* CPLD Timing parameters for IFC GPCM */
145 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
146                                         FTIM0_GPCM_TEADC(0xf) | \
147                                         FTIM0_GPCM_TEAHC(0xf))
148 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
149                                         FTIM1_GPCM_TRAD(0x3f))
150 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
151                                         FTIM2_GPCM_TCH(0xf) | \
152                                         FTIM2_GPCM_TWP(0xff))
153 #define CONFIG_SYS_FPGA_FTIM3           0x0
154 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
155 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
156 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
157 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
158 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
159 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
160 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
161 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
162 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
163 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
164 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
165 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
166 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
167 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
168 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
169 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
170
171 /*
172  * Serial Port
173  */
174 #ifdef CONFIG_LPUART
175 #define CONFIG_LPUART_32B_REG
176 #else
177 #define CONFIG_SYS_NS16550_SERIAL
178 #ifndef CONFIG_DM_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE     1
180 #endif
181 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
182 #endif
183
184 /*
185  * I2C
186  */
187
188 /* GPIO */
189
190 /* EEPROM */
191 #define CONFIG_SYS_I2C_EEPROM_NXID
192 #define CONFIG_SYS_EEPROM_BUS_NUM               1
193
194 /*
195  * MMC
196  */
197
198 /*
199  * Video
200  */
201 #ifdef CONFIG_VIDEO_FSL_DCU_FB
202 #define CONFIG_VIDEO_LOGO
203 #define CONFIG_VIDEO_BMP_LOGO
204
205 #define CONFIG_FSL_DCU_SII9022A
206 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
207 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
208 #endif
209
210 /*
211  * eTSEC
212  */
213
214 #ifdef CONFIG_TSEC_ENET
215 #define CONFIG_ETHPRIME                 "ethernet@2d10000"
216 #endif
217
218 /* PCIe */
219 #define CONFIG_PCIE1            /* PCIE controller 1 */
220 #define CONFIG_PCIE2            /* PCIE controller 2 */
221
222 #ifdef CONFIG_PCI
223 #define CONFIG_PCI_SCAN_SHOW
224 #endif
225
226 #define CONFIG_PEN_ADDR_BIG_ENDIAN
227 #define CONFIG_LAYERSCAPE_NS_ACCESS
228 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
229 #define COUNTER_FREQUENCY               12500000
230
231 #define CONFIG_HWCONFIG
232 #define HWCONFIG_BUFFER_SIZE            256
233
234 #define CONFIG_FSL_DEVICE_DISABLE
235
236 #define BOOT_TARGET_DEVICES(func) \
237         func(MMC, mmc, 0) \
238         func(USB, usb, 0) \
239         func(DHCP, dhcp, na)
240 #include <config_distro_bootcmd.h>
241
242 #ifdef CONFIG_LPUART
243 #define CONFIG_EXTRA_ENV_SETTINGS       \
244         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
245                 "cma=64M@0x0-0xb0000000\0" \
246         "initrd_high=0xffffffff\0"      \
247         "fdt_addr=0x64f00000\0"         \
248         "kernel_addr=0x65000000\0"      \
249         "scriptaddr=0x80000000\0"       \
250         "scripthdraddr=0x80080000\0"    \
251         "fdtheader_addr_r=0x80100000\0" \
252         "kernelheader_addr_r=0x80200000\0"      \
253         "kernel_addr_r=0x81000000\0"    \
254         "fdt_addr_r=0x90000000\0"       \
255         "ramdisk_addr_r=0xa0000000\0"   \
256         "load_addr=0xa0000000\0"        \
257         "kernel_size=0x2800000\0"       \
258         "kernel_addr_sd=0x8000\0"       \
259         "kernel_size_sd=0x14000\0"      \
260         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
261         BOOTENV                         \
262         "boot_scripts=ls1021atwr_boot.scr\0"    \
263         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
264                 "scan_dev_for_boot_part="       \
265                         "part list ${devtype} ${devnum} devplist; "     \
266                         "env exists devplist || setenv devplist 1; "    \
267                         "for distro_bootpart in ${devplist}; do "       \
268                         "if fstype ${devtype} "                         \
269                                 "${devnum}:${distro_bootpart} "         \
270                                 "bootfstype; then "                     \
271                                 "run scan_dev_for_boot; "               \
272                         "fi; "                  \
273                 "done\0"                        \
274         "scan_dev_for_boot="                              \
275                 "echo Scanning ${devtype} "               \
276                                 "${devnum}:${distro_bootpart}...; "  \
277                 "for prefix in ${boot_prefixes}; do "     \
278                         "run scan_dev_for_scripts; "      \
279                 "done;"                                   \
280                 "\0"                                      \
281         "boot_a_script="                                  \
282                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
283                         "${scriptaddr} ${prefix}${script}; "    \
284                 "env exists secureboot && load ${devtype} "     \
285                         "${devnum}:${distro_bootpart} "         \
286                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
287                         "env exists secureboot "        \
288                         "&& esbc_validate ${scripthdraddr};"    \
289                 "source ${scriptaddr}\0"          \
290         "installer=load mmc 0:2 $load_addr "    \
291                 "/flex_installer_arm32.itb; "           \
292                 "bootm $load_addr#ls1021atwr\0" \
293         "qspi_bootcmd=echo Trying load from qspi..;"    \
294                 "sf probe && sf read $load_addr "       \
295                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
296         "nor_bootcmd=echo Trying load from nor..;"      \
297                 "cp.b $kernel_addr $load_addr "         \
298                 "$kernel_size && bootm $load_addr#$board\0"
299 #else
300 #define CONFIG_EXTRA_ENV_SETTINGS       \
301         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
302                 "cma=64M@0x0-0xb0000000\0" \
303         "initrd_high=0xffffffff\0"      \
304         "fdt_addr=0x64f00000\0"         \
305         "kernel_addr=0x61000000\0"      \
306         "kernelheader_addr=0x60800000\0"        \
307         "scriptaddr=0x80000000\0"       \
308         "scripthdraddr=0x80080000\0"    \
309         "fdtheader_addr_r=0x80100000\0" \
310         "kernelheader_addr_r=0x80200000\0"      \
311         "kernel_addr_r=0x81000000\0"    \
312         "kernelheader_size=0x40000\0"   \
313         "fdt_addr_r=0x90000000\0"       \
314         "ramdisk_addr_r=0xa0000000\0"   \
315         "load_addr=0xa0000000\0"        \
316         "kernel_size=0x2800000\0"       \
317         "kernel_addr_sd=0x8000\0"       \
318         "kernel_size_sd=0x14000\0"      \
319         "kernelhdr_addr_sd=0x4000\0"            \
320         "kernelhdr_size_sd=0x10\0"              \
321         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
322         BOOTENV                         \
323         "boot_scripts=ls1021atwr_boot.scr\0"    \
324         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
325                 "scan_dev_for_boot_part="       \
326                         "part list ${devtype} ${devnum} devplist; "     \
327                         "env exists devplist || setenv devplist 1; "    \
328                         "for distro_bootpart in ${devplist}; do "       \
329                         "if fstype ${devtype} "                         \
330                                 "${devnum}:${distro_bootpart} "         \
331                                 "bootfstype; then "                     \
332                                 "run scan_dev_for_boot; "               \
333                         "fi; "                  \
334                 "done\0"                        \
335         "scan_dev_for_boot="                              \
336                 "echo Scanning ${devtype} "               \
337                                 "${devnum}:${distro_bootpart}...; "  \
338                 "for prefix in ${boot_prefixes}; do "     \
339                         "run scan_dev_for_scripts; "      \
340                 "done;"                                   \
341                 "\0"                                      \
342         "boot_a_script="                                  \
343                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
344                         "${scriptaddr} ${prefix}${script}; "    \
345                 "env exists secureboot && load ${devtype} "     \
346                         "${devnum}:${distro_bootpart} "         \
347                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
348                         "&& esbc_validate ${scripthdraddr};"    \
349                 "source ${scriptaddr}\0"          \
350         "qspi_bootcmd=echo Trying load from qspi..;"    \
351                 "sf probe && sf read $load_addr "       \
352                 "$kernel_addr $kernel_size; env exists secureboot "     \
353                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
354                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
355                 "bootm $load_addr#$board\0" \
356         "nor_bootcmd=echo Trying load from nor..;"      \
357                 "cp.b $kernel_addr $load_addr "         \
358                 "$kernel_size; env exists secureboot "  \
359                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
360                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
361                 "bootm $load_addr#$board\0"     \
362         "sd_bootcmd=echo Trying load from SD ..;"       \
363                 "mmcinfo && mmc read $load_addr "       \
364                 "$kernel_addr_sd $kernel_size_sd && "   \
365                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
366                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
367                 " && esbc_validate ${kernelheader_addr_r};"     \
368                 "bootm $load_addr#$board\0"
369 #endif
370
371 /*
372  * Miscellaneous configurable options
373  */
374 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
375
376 #define CONFIG_LS102XA_STREAM_ID
377
378 #define CONFIG_SYS_INIT_SP_OFFSET \
379         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
380 #define CONFIG_SYS_INIT_SP_ADDR \
381         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
382
383 #ifdef CONFIG_SPL_BUILD
384 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
385 #else
386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
387 #endif
388
389 /*
390  * Environment
391  */
392
393 #include <asm/fsl_secure_boot.h>
394 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
395
396 #endif