include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DEEP_SLEEP
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 #define DDR_SDRAM_CFG                   0x470c0008
  16 #define DDR_CS0_BNDS                    0x008000bf
  17 #define DDR_CS0_CONFIG                  0x80014302
  18 #define DDR_TIMING_CFG_0                0x50550004
  19 #define DDR_TIMING_CFG_1                0xbcb38c56
  20 #define DDR_TIMING_CFG_2                0x0040d120
  21 #define DDR_TIMING_CFG_3                0x010e1000
  22 #define DDR_TIMING_CFG_4                0x00000001
  23 #define DDR_TIMING_CFG_5                0x03401400
  24 #define DDR_SDRAM_CFG_2                 0x00401010
  25 #define DDR_SDRAM_MODE                  0x00061c60
  26 #define DDR_SDRAM_MODE_2                0x00180000
  27 #define DDR_SDRAM_INTERVAL              0x18600618
  28 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  29 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  30 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  31 #define DDR_DDR_CDR1                    0x80040000
  32 #define DDR_DDR_CDR2                    0x00000001
  33 #define DDR_SDRAM_CLK_CNTL              0x02000000
  34 #define DDR_DDR_ZQ_CNTL                 0x89080600
  35 #define DDR_CS0_CONFIG_2                0
  36 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  37 #define SDRAM_CFG2_D_INIT               0x00000010
  38 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  39 #define SDRAM_CFG2_FRC_SR               0x80000000
  40 #define SDRAM_CFG_BI                    0x00000001
  41
  42 #ifdef CONFIG_SD_BOOT
  43 #ifdef CONFIG_NXP_ESBC
  44 /*
  45  * HDR would be appended at end of image and copied to DDR along
  46  * with U-Boot image.
  47  */
  48 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  49 #endif /* ifdef CONFIG_NXP_ESBC */
  50
  51 #define CONFIG_SPL_MAX_SIZE             0x1a000
  52 #define CONFIG_SPL_STACK                0x1001d000
  53 #define CONFIG_SPL_PAD_TO               0x1c000
  54
  55 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  56                 CONFIG_SYS_MONITOR_LEN)
  57 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  58 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  59 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  60
  61 #ifdef CONFIG_U_BOOT_HDR_SIZE
  62 /*
  63  * HDR would be appended at end of image and copied to DDR along
  64  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  65  * size increases then increase this size in case of secure boot as
  66  * it uses raw u-boot image instead of fit image.
  67  */
  68 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  69 #else
  70 #define CONFIG_SYS_MONITOR_LEN          0x100000
  71 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  72 #endif
  73
  74 #define PHYS_SDRAM                      0x80000000
  75 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  76
  77 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  78 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  79
  80 /*
  81  * IFC Definitions
  82  */
  83 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  84 #define CONFIG_SYS_FLASH_BASE           0x60000000
  85 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  86
  87 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  88 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  89                                 CSPR_PORT_SIZE_16 | \
  90                                 CSPR_MSEL_NOR | \
  91                                 CSPR_V)
  92 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  93
  94 /* NOR Flash Timing Params */
  95 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  96                                         CSOR_NOR_TRHZ_80)
  97 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  98                                         FTIM0_NOR_TEADC(0x5) | \
  99                                         FTIM0_NOR_TAVDS(0x0) | \
 100                                         FTIM0_NOR_TEAHC(0x5))
 101 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 102                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 103                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 104 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 105                                         FTIM2_NOR_TCH(0x4) | \
 106                                         FTIM2_NOR_TWP(0x1c) | \
 107                                         FTIM2_NOR_TWPH(0x0e))
 108 #define CONFIG_SYS_NOR_FTIM3            0
 109
 110 #define CONFIG_SYS_FLASH_QUIET_TEST
 111 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 112
 113 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 114 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 115 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 116
 117 #define CONFIG_SYS_FLASH_EMPTY_INFO
 118 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 119
 120 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 121 #endif
 122
 123 /* CPLD */
 124
 125 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 126 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 127
 128 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 129 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 130                                         CSPR_PORT_SIZE_8 | \
 131                                         CSPR_MSEL_GPCM | \
 132                                         CSPR_V)
 133 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 134 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 135                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 136                                         CSOR_NOR_TRHZ_80)
 137
 138 /* CPLD Timing parameters for IFC GPCM */
 139 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 140                                         FTIM0_GPCM_TEADC(0xf) | \
 141                                         FTIM0_GPCM_TEAHC(0xf))
 142 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 143                                         FTIM1_GPCM_TRAD(0x3f))
 144 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 145                                         FTIM2_GPCM_TCH(0xf) | \
 146                                         FTIM2_GPCM_TWP(0xff))
 147 #define CONFIG_SYS_FPGA_FTIM3           0x0
 148 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 149 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 150 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 151 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 152 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 153 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 154 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 155 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 156 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 157 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 158 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 159 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 160 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 161 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 162 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 163 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 164
 165 /*
 166  * Serial Port
 167  */
 168 #ifdef CONFIG_LPUART
 169 #define CONFIG_LPUART_32B_REG
 170 #else
 171 #define CONFIG_SYS_NS16550_SERIAL
 172 #ifndef CONFIG_DM_SERIAL
 173 #define CONFIG_SYS_NS16550_REG_SIZE     1
 174 #endif
 175 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 176 #endif
 177
 178 /*
 179  * I2C
 180  */
 181
 182 /* GPIO */
 183
 184 /* EEPROM */
 185 #define CONFIG_SYS_I2C_EEPROM_NXID
 186 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 187
 188 /*
 189  * MMC
 190  */
 191
 192 /*
 193  * Video
 194  */
 195 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 196 #define CONFIG_VIDEO_BMP_LOGO
 197
 198 #define CONFIG_FSL_DCU_SII9022A
 199 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 200 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 201 #endif
 202
 203 /*
 204  * eTSEC
 205  */
 206
 207 #ifdef CONFIG_TSEC_ENET
 208 #define CONFIG_ETHPRIME                 "ethernet@2d10000"
 209 #endif
 210
 211 /* PCIe */
 212 #define CONFIG_PCIE1            /* PCIE controller 1 */
 213 #define CONFIG_PCIE2            /* PCIE controller 2 */
 214
 215 #ifdef CONFIG_PCI
 216 #define CONFIG_PCI_SCAN_SHOW
 217 #endif
 218
 219 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 220 #define CONFIG_LAYERSCAPE_NS_ACCESS
 221 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 222 #define COUNTER_FREQUENCY               12500000
 223
 224 #define CONFIG_HWCONFIG
 225 #define HWCONFIG_BUFFER_SIZE            256
 226
 227 #define CONFIG_FSL_DEVICE_DISABLE
 228
 229 #define BOOT_TARGET_DEVICES(func) \
 230         func(MMC, mmc, 0) \
 231         func(USB, usb, 0) \
 232         func(DHCP, dhcp, na)
 233 #include <config_distro_bootcmd.h>
 234
 235 #ifdef CONFIG_LPUART
 236 #define CONFIG_EXTRA_ENV_SETTINGS       \
 237         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 238                 "cma=64M@0x0-0xb0000000\0" \
 239         "initrd_high=0xffffffff\0"      \
 240         "fdt_addr=0x64f00000\0"         \
 241         "kernel_addr=0x65000000\0"      \
 242         "scriptaddr=0x80000000\0"       \
 243         "scripthdraddr=0x80080000\0"    \
 244         "fdtheader_addr_r=0x80100000\0" \
 245         "kernelheader_addr_r=0x80200000\0"      \
 246         "kernel_addr_r=0x81000000\0"    \
 247         "fdt_addr_r=0x90000000\0"       \
 248         "ramdisk_addr_r=0xa0000000\0"   \
 249         "load_addr=0xa0000000\0"        \
 250         "kernel_size=0x2800000\0"       \
 251         "kernel_addr_sd=0x8000\0"       \
 252         "kernel_size_sd=0x14000\0"      \
 253         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 254         BOOTENV                         \
 255         "boot_scripts=ls1021atwr_boot.scr\0"    \
 256         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 257                 "scan_dev_for_boot_part="       \
 258                         "part list ${devtype} ${devnum} devplist; "     \
 259                         "env exists devplist || setenv devplist 1; "    \
 260                         "for distro_bootpart in ${devplist}; do "       \
 261                         "if fstype ${devtype} "                         \
 262                                 "${devnum}:${distro_bootpart} "         \
 263                                 "bootfstype; then "                     \
 264                                 "run scan_dev_for_boot; "               \
 265                         "fi; "                  \
 266                 "done\0"                        \
 267         "scan_dev_for_boot="                              \
 268                 "echo Scanning ${devtype} "               \
 269                                 "${devnum}:${distro_bootpart}...; "  \
 270                 "for prefix in ${boot_prefixes}; do "     \
 271                         "run scan_dev_for_scripts; "      \
 272                 "done;"                                   \
 273                 "\0"                                      \
 274         "boot_a_script="                                  \
 275                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 276                         "${scriptaddr} ${prefix}${script}; "    \
 277                 "env exists secureboot && load ${devtype} "     \
 278                         "${devnum}:${distro_bootpart} "         \
 279                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 280                         "env exists secureboot "        \
 281                         "&& esbc_validate ${scripthdraddr};"    \
 282                 "source ${scriptaddr}\0"          \
 283         "installer=load mmc 0:2 $load_addr "    \
 284                 "/flex_installer_arm32.itb; "           \
 285                 "bootm $load_addr#ls1021atwr\0" \
 286         "qspi_bootcmd=echo Trying load from qspi..;"    \
 287                 "sf probe && sf read $load_addr "       \
 288                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 289         "nor_bootcmd=echo Trying load from nor..;"      \
 290                 "cp.b $kernel_addr $load_addr "         \
 291                 "$kernel_size && bootm $load_addr#$board\0"
 292 #else
 293 #define CONFIG_EXTRA_ENV_SETTINGS       \
 294         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 295                 "cma=64M@0x0-0xb0000000\0" \
 296         "initrd_high=0xffffffff\0"      \
 297         "fdt_addr=0x64f00000\0"         \
 298         "kernel_addr=0x61000000\0"      \
 299         "kernelheader_addr=0x60800000\0"        \
 300         "scriptaddr=0x80000000\0"       \
 301         "scripthdraddr=0x80080000\0"    \
 302         "fdtheader_addr_r=0x80100000\0" \
 303         "kernelheader_addr_r=0x80200000\0"      \
 304         "kernel_addr_r=0x81000000\0"    \
 305         "kernelheader_size=0x40000\0"   \
 306         "fdt_addr_r=0x90000000\0"       \
 307         "ramdisk_addr_r=0xa0000000\0"   \
 308         "load_addr=0xa0000000\0"        \
 309         "kernel_size=0x2800000\0"       \
 310         "kernel_addr_sd=0x8000\0"       \
 311         "kernel_size_sd=0x14000\0"      \
 312         "kernelhdr_addr_sd=0x4000\0"            \
 313         "kernelhdr_size_sd=0x10\0"              \
 314         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 315         BOOTENV                         \
 316         "boot_scripts=ls1021atwr_boot.scr\0"    \
 317         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 318                 "scan_dev_for_boot_part="       \
 319                         "part list ${devtype} ${devnum} devplist; "     \
 320                         "env exists devplist || setenv devplist 1; "    \
 321                         "for distro_bootpart in ${devplist}; do "       \
 322                         "if fstype ${devtype} "                         \
 323                                 "${devnum}:${distro_bootpart} "         \
 324                                 "bootfstype; then "                     \
 325                                 "run scan_dev_for_boot; "               \
 326                         "fi; "                  \
 327                 "done\0"                        \
 328         "scan_dev_for_boot="                              \
 329                 "echo Scanning ${devtype} "               \
 330                                 "${devnum}:${distro_bootpart}...; "  \
 331                 "for prefix in ${boot_prefixes}; do "     \
 332                         "run scan_dev_for_scripts; "      \
 333                 "done;"                                   \
 334                 "\0"                                      \
 335         "boot_a_script="                                  \
 336                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 337                         "${scriptaddr} ${prefix}${script}; "    \
 338                 "env exists secureboot && load ${devtype} "     \
 339                         "${devnum}:${distro_bootpart} "         \
 340                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 341                         "&& esbc_validate ${scripthdraddr};"    \
 342                 "source ${scriptaddr}\0"          \
 343         "qspi_bootcmd=echo Trying load from qspi..;"    \
 344                 "sf probe && sf read $load_addr "       \
 345                 "$kernel_addr $kernel_size; env exists secureboot "     \
 346                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 347                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 348                 "bootm $load_addr#$board\0" \
 349         "nor_bootcmd=echo Trying load from nor..;"      \
 350                 "cp.b $kernel_addr $load_addr "         \
 351                 "$kernel_size; env exists secureboot "  \
 352                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 353                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 354                 "bootm $load_addr#$board\0"     \
 355         "sd_bootcmd=echo Trying load from SD ..;"       \
 356                 "mmcinfo && mmc read $load_addr "       \
 357                 "$kernel_addr_sd $kernel_size_sd && "   \
 358                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 359                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 360                 " && esbc_validate ${kernelheader_addr_r};"     \
 361                 "bootm $load_addr#$board\0"
 362 #endif
 363
 364 /*
 365  * Miscellaneous configurable options
 366  */
 367 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 368
 369 #define CONFIG_LS102XA_STREAM_ID
 370
 371 #define CONFIG_SYS_INIT_SP_OFFSET \
 372         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 373 #define CONFIG_SYS_INIT_SP_ADDR \
 374         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 375
 376 #ifdef CONFIG_SPL_BUILD
 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 378 #else
 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 380 #endif
 381
 382 /*
 383  * Environment
 384  */
 385
 386 #include <asm/fsl_secure_boot.h>
 387 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 388
 389 #endif