Convert CONFIG_ESDHC_DETECT_QUIRK to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls1021atwr.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2019, 2021 NXP
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
12
13 #define DDR_SDRAM_CFG                   0x470c0008
14 #define DDR_CS0_BNDS                    0x008000bf
15 #define DDR_CS0_CONFIG                  0x80014302
16 #define DDR_TIMING_CFG_0                0x50550004
17 #define DDR_TIMING_CFG_1                0xbcb38c56
18 #define DDR_TIMING_CFG_2                0x0040d120
19 #define DDR_TIMING_CFG_3                0x010e1000
20 #define DDR_TIMING_CFG_4                0x00000001
21 #define DDR_TIMING_CFG_5                0x03401400
22 #define DDR_SDRAM_CFG_2                 0x00401010
23 #define DDR_SDRAM_MODE                  0x00061c60
24 #define DDR_SDRAM_MODE_2                0x00180000
25 #define DDR_SDRAM_INTERVAL              0x18600618
26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
29 #define DDR_DDR_CDR1                    0x80040000
30 #define DDR_DDR_CDR2                    0x00000001
31 #define DDR_SDRAM_CLK_CNTL              0x02000000
32 #define DDR_DDR_ZQ_CNTL                 0x89080600
33 #define DDR_CS0_CONFIG_2                0
34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
35 #define SDRAM_CFG2_D_INIT               0x00000010
36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
37 #define SDRAM_CFG2_FRC_SR               0x80000000
38 #define SDRAM_CFG_BI                    0x00000001
39
40 #ifdef CONFIG_SD_BOOT
41 #ifdef CONFIG_NXP_ESBC
42 /*
43  * HDR would be appended at end of image and copied to DDR along
44  * with U-Boot image.
45  */
46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
47 #endif /* ifdef CONFIG_NXP_ESBC */
48
49 #ifdef CONFIG_U_BOOT_HDR_SIZE
50 /*
51  * HDR would be appended at end of image and copied to DDR along
52  * with U-Boot image. Here u-boot max. size is 512K. So if binary
53  * size increases then increase this size in case of secure boot as
54  * it uses raw u-boot image instead of fit image.
55  */
56 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
57 #else
58 #define CONFIG_SYS_MONITOR_LEN          0x100000
59 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
60 #endif
61
62 #define PHYS_SDRAM                      0x80000000
63 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
64
65 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
66 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
67
68 /*
69  * IFC Definitions
70  */
71 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
72 #define CONFIG_SYS_FLASH_BASE           0x60000000
73 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
74
75 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
76 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
77                                 CSPR_PORT_SIZE_16 | \
78                                 CSPR_MSEL_NOR | \
79                                 CSPR_V)
80 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
81
82 /* NOR Flash Timing Params */
83 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
84                                         CSOR_NOR_TRHZ_80)
85 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
86                                         FTIM0_NOR_TEADC(0x5) | \
87                                         FTIM0_NOR_TAVDS(0x0) | \
88                                         FTIM0_NOR_TEAHC(0x5))
89 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
90                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
91                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
92 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
93                                         FTIM2_NOR_TCH(0x4) | \
94                                         FTIM2_NOR_TWP(0x1c) | \
95                                         FTIM2_NOR_TWPH(0x0e))
96 #define CONFIG_SYS_NOR_FTIM3            0
97
98 #define CONFIG_SYS_FLASH_QUIET_TEST
99 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
100
101 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
102 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
103 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
104
105 #define CONFIG_SYS_FLASH_EMPTY_INFO
106 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
107
108 #define CONFIG_SYS_WRITE_SWAPPED_DATA
109 #endif
110
111 /* CPLD */
112
113 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
114 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
115
116 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
117 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
118                                         CSPR_PORT_SIZE_8 | \
119                                         CSPR_MSEL_GPCM | \
120                                         CSPR_V)
121 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
122 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
123                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
124                                         CSOR_NOR_TRHZ_80)
125
126 /* CPLD Timing parameters for IFC GPCM */
127 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
128                                         FTIM0_GPCM_TEADC(0xf) | \
129                                         FTIM0_GPCM_TEAHC(0xf))
130 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
131                                         FTIM1_GPCM_TRAD(0x3f))
132 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
133                                         FTIM2_GPCM_TCH(0xf) | \
134                                         FTIM2_GPCM_TWP(0xff))
135 #define CONFIG_SYS_FPGA_FTIM3           0x0
136 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
137 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
138 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
139 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
140 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
141 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
142 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
143 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
144 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
145 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
146 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
147 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
148 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
149 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
150 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
151 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
152
153 /*
154  * Serial Port
155  */
156 #ifndef CONFIG_LPUART
157 #define CONFIG_SYS_NS16550_SERIAL
158 #ifndef CONFIG_DM_SERIAL
159 #define CONFIG_SYS_NS16550_REG_SIZE     1
160 #endif
161 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
162 #endif
163
164 /*
165  * I2C
166  */
167
168 /* GPIO */
169
170 /* EEPROM */
171 #define CONFIG_SYS_I2C_EEPROM_NXID
172 #define CONFIG_SYS_EEPROM_BUS_NUM               1
173
174 /* PCIe */
175 #define CONFIG_PCIE1            /* PCIE controller 1 */
176 #define CONFIG_PCIE2            /* PCIE controller 2 */
177
178 #ifdef CONFIG_PCI
179 #define CONFIG_PCI_SCAN_SHOW
180 #endif
181
182 #define CONFIG_PEN_ADDR_BIG_ENDIAN
183 #define CONFIG_LAYERSCAPE_NS_ACCESS
184 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
185
186 #define CONFIG_HWCONFIG
187 #define HWCONFIG_BUFFER_SIZE            256
188
189 #define CONFIG_FSL_DEVICE_DISABLE
190
191 #define BOOT_TARGET_DEVICES(func) \
192         func(MMC, mmc, 0) \
193         func(USB, usb, 0) \
194         func(DHCP, dhcp, na)
195 #include <config_distro_bootcmd.h>
196
197 #ifdef CONFIG_LPUART
198 #define CONFIG_EXTRA_ENV_SETTINGS       \
199         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
200                 "cma=64M@0x0-0xb0000000\0" \
201         "initrd_high=0xffffffff\0"      \
202         "kernel_addr=0x65000000\0"      \
203         "scriptaddr=0x80000000\0"       \
204         "scripthdraddr=0x80080000\0"    \
205         "fdtheader_addr_r=0x80100000\0" \
206         "kernelheader_addr_r=0x80200000\0"      \
207         "kernel_addr_r=0x81000000\0"    \
208         "fdt_addr_r=0x90000000\0"       \
209         "ramdisk_addr_r=0xa0000000\0"   \
210         "load_addr=0xa0000000\0"        \
211         "kernel_size=0x2800000\0"       \
212         "kernel_addr_sd=0x8000\0"       \
213         "kernel_size_sd=0x14000\0"      \
214         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
215         BOOTENV                         \
216         "boot_scripts=ls1021atwr_boot.scr\0"    \
217         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
218                 "scan_dev_for_boot_part="       \
219                         "part list ${devtype} ${devnum} devplist; "     \
220                         "env exists devplist || setenv devplist 1; "    \
221                         "for distro_bootpart in ${devplist}; do "       \
222                         "if fstype ${devtype} "                         \
223                                 "${devnum}:${distro_bootpart} "         \
224                                 "bootfstype; then "                     \
225                                 "run scan_dev_for_boot; "               \
226                         "fi; "                  \
227                 "done\0"                        \
228         "scan_dev_for_boot="                              \
229                 "echo Scanning ${devtype} "               \
230                                 "${devnum}:${distro_bootpart}...; "  \
231                 "for prefix in ${boot_prefixes}; do "     \
232                         "run scan_dev_for_scripts; "      \
233                 "done;"                                   \
234                 "\0"                                      \
235         "boot_a_script="                                  \
236                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
237                         "${scriptaddr} ${prefix}${script}; "    \
238                 "env exists secureboot && load ${devtype} "     \
239                         "${devnum}:${distro_bootpart} "         \
240                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
241                         "env exists secureboot "        \
242                         "&& esbc_validate ${scripthdraddr};"    \
243                 "source ${scriptaddr}\0"          \
244         "installer=load mmc 0:2 $load_addr "    \
245                 "/flex_installer_arm32.itb; "           \
246                 "bootm $load_addr#ls1021atwr\0" \
247         "qspi_bootcmd=echo Trying load from qspi..;"    \
248                 "sf probe && sf read $load_addr "       \
249                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
250         "nor_bootcmd=echo Trying load from nor..;"      \
251                 "cp.b $kernel_addr $load_addr "         \
252                 "$kernel_size && bootm $load_addr#$board\0"
253 #else
254 #define CONFIG_EXTRA_ENV_SETTINGS       \
255         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
256                 "cma=64M@0x0-0xb0000000\0" \
257         "initrd_high=0xffffffff\0"      \
258         "kernel_addr=0x61000000\0"      \
259         "kernelheader_addr=0x60800000\0"        \
260         "scriptaddr=0x80000000\0"       \
261         "scripthdraddr=0x80080000\0"    \
262         "fdtheader_addr_r=0x80100000\0" \
263         "kernelheader_addr_r=0x80200000\0"      \
264         "kernel_addr_r=0x81000000\0"    \
265         "kernelheader_size=0x40000\0"   \
266         "fdt_addr_r=0x90000000\0"       \
267         "ramdisk_addr_r=0xa0000000\0"   \
268         "load_addr=0xa0000000\0"        \
269         "kernel_size=0x2800000\0"       \
270         "kernel_addr_sd=0x8000\0"       \
271         "kernel_size_sd=0x14000\0"      \
272         "kernelhdr_addr_sd=0x4000\0"            \
273         "kernelhdr_size_sd=0x10\0"              \
274         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
275         BOOTENV                         \
276         "boot_scripts=ls1021atwr_boot.scr\0"    \
277         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
278                 "scan_dev_for_boot_part="       \
279                         "part list ${devtype} ${devnum} devplist; "     \
280                         "env exists devplist || setenv devplist 1; "    \
281                         "for distro_bootpart in ${devplist}; do "       \
282                         "if fstype ${devtype} "                         \
283                                 "${devnum}:${distro_bootpart} "         \
284                                 "bootfstype; then "                     \
285                                 "run scan_dev_for_boot; "               \
286                         "fi; "                  \
287                 "done\0"                        \
288         "scan_dev_for_boot="                              \
289                 "echo Scanning ${devtype} "               \
290                                 "${devnum}:${distro_bootpart}...; "  \
291                 "for prefix in ${boot_prefixes}; do "     \
292                         "run scan_dev_for_scripts; "      \
293                 "done;"                                   \
294                 "\0"                                      \
295         "boot_a_script="                                  \
296                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
297                         "${scriptaddr} ${prefix}${script}; "    \
298                 "env exists secureboot && load ${devtype} "     \
299                         "${devnum}:${distro_bootpart} "         \
300                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
301                         "&& esbc_validate ${scripthdraddr};"    \
302                 "source ${scriptaddr}\0"          \
303         "qspi_bootcmd=echo Trying load from qspi..;"    \
304                 "sf probe && sf read $load_addr "       \
305                 "$kernel_addr $kernel_size; env exists secureboot "     \
306                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
307                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
308                 "bootm $load_addr#$board\0" \
309         "nor_bootcmd=echo Trying load from nor..;"      \
310                 "cp.b $kernel_addr $load_addr "         \
311                 "$kernel_size; env exists secureboot "  \
312                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
313                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
314                 "bootm $load_addr#$board\0"     \
315         "sd_bootcmd=echo Trying load from SD ..;"       \
316                 "mmcinfo && mmc read $load_addr "       \
317                 "$kernel_addr_sd $kernel_size_sd && "   \
318                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
319                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
320                 " && esbc_validate ${kernelheader_addr_r};"     \
321                 "bootm $load_addr#$board\0"
322 #endif
323
324 /*
325  * Miscellaneous configurable options
326  */
327 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
328
329 #define CONFIG_LS102XA_STREAM_ID
330
331 /*
332  * Environment
333  */
334
335 #include <asm/fsl_secure_boot.h>
336 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
337
338 #endif