1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2019, 2021 NXP
10 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
13 #define DDR_SDRAM_CFG 0x470c0008
14 #define DDR_CS0_BNDS 0x008000bf
15 #define DDR_CS0_CONFIG 0x80014302
16 #define DDR_TIMING_CFG_0 0x50550004
17 #define DDR_TIMING_CFG_1 0xbcb38c56
18 #define DDR_TIMING_CFG_2 0x0040d120
19 #define DDR_TIMING_CFG_3 0x010e1000
20 #define DDR_TIMING_CFG_4 0x00000001
21 #define DDR_TIMING_CFG_5 0x03401400
22 #define DDR_SDRAM_CFG_2 0x00401010
23 #define DDR_SDRAM_MODE 0x00061c60
24 #define DDR_SDRAM_MODE_2 0x00180000
25 #define DDR_SDRAM_INTERVAL 0x18600618
26 #define DDR_DDR_WRLVL_CNTL 0x8655f605
27 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
28 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
29 #define DDR_DDR_CDR1 0x80040000
30 #define DDR_DDR_CDR2 0x00000001
31 #define DDR_SDRAM_CLK_CNTL 0x02000000
32 #define DDR_DDR_ZQ_CNTL 0x89080600
33 #define DDR_CS0_CONFIG_2 0
34 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
35 #define SDRAM_CFG2_D_INIT 0x00000010
36 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
37 #define SDRAM_CFG2_FRC_SR 0x80000000
38 #define SDRAM_CFG_BI 0x00000001
41 #ifdef CONFIG_NXP_ESBC
43 * HDR would be appended at end of image and copied to DDR along
46 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
47 #endif /* ifdef CONFIG_NXP_ESBC */
49 #ifdef CONFIG_U_BOOT_HDR_SIZE
51 * HDR would be appended at end of image and copied to DDR along
52 * with U-Boot image. Here u-boot max. size is 512K. So if binary
53 * size increases then increase this size in case of secure boot as
54 * it uses raw u-boot image instead of fit image.
56 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
58 #define CONFIG_SYS_MONITOR_LEN 0x100000
59 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
62 #define PHYS_SDRAM 0x80000000
63 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
65 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
72 #define CONFIG_SYS_FLASH_BASE 0x60000000
73 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
75 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
76 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
80 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
82 /* NOR Flash Timing Params */
83 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
85 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
86 FTIM0_NOR_TEADC(0x5) | \
87 FTIM0_NOR_TAVDS(0x0) | \
89 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
90 FTIM1_NOR_TRAD_NOR(0x1A) | \
91 FTIM1_NOR_TSEQRAD_NOR(0x13))
92 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
93 FTIM2_NOR_TCH(0x4) | \
94 FTIM2_NOR_TWP(0x1c) | \
96 #define CONFIG_SYS_NOR_FTIM3 0
98 #define CONFIG_SYS_FLASH_QUIET_TEST
99 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
101 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
102 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
103 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
105 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
107 #define CONFIG_SYS_WRITE_SWAPPED_DATA
112 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
113 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
115 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
116 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
120 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
121 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
122 CSOR_NOR_NOR_MODE_AVD_NOR | \
125 /* CPLD Timing parameters for IFC GPCM */
126 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
127 FTIM0_GPCM_TEADC(0xf) | \
128 FTIM0_GPCM_TEAHC(0xf))
129 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
130 FTIM1_GPCM_TRAD(0x3f))
131 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
132 FTIM2_GPCM_TCH(0xf) | \
133 FTIM2_GPCM_TWP(0xff))
134 #define CONFIG_SYS_FPGA_FTIM3 0x0
135 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
136 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
137 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
138 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
139 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
140 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
141 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
142 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
143 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
144 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
145 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
146 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
147 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
148 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
149 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
150 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
155 #ifndef CONFIG_LPUART
156 #define CONFIG_SYS_NS16550_SERIAL
157 #ifndef CONFIG_DM_SERIAL
158 #define CONFIG_SYS_NS16550_REG_SIZE 1
160 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
170 #define CONFIG_SYS_I2C_EEPROM_NXID
171 #define CONFIG_SYS_EEPROM_BUS_NUM 1
173 #define CONFIG_PEN_ADDR_BIG_ENDIAN
174 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
176 #define CONFIG_HWCONFIG
177 #define HWCONFIG_BUFFER_SIZE 256
179 #define CONFIG_FSL_DEVICE_DISABLE
181 #define BOOT_TARGET_DEVICES(func) \
185 #include <config_distro_bootcmd.h>
188 #define CONFIG_EXTRA_ENV_SETTINGS \
189 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
190 "cma=64M@0x0-0xb0000000\0" \
191 "initrd_high=0xffffffff\0" \
192 "kernel_addr=0x65000000\0" \
193 "scriptaddr=0x80000000\0" \
194 "scripthdraddr=0x80080000\0" \
195 "fdtheader_addr_r=0x80100000\0" \
196 "kernelheader_addr_r=0x80200000\0" \
197 "kernel_addr_r=0x81000000\0" \
198 "fdt_addr_r=0x90000000\0" \
199 "ramdisk_addr_r=0xa0000000\0" \
200 "load_addr=0xa0000000\0" \
201 "kernel_size=0x2800000\0" \
202 "kernel_addr_sd=0x8000\0" \
203 "kernel_size_sd=0x14000\0" \
204 "othbootargs=cma=64M@0x0-0xb0000000\0" \
206 "boot_scripts=ls1021atwr_boot.scr\0" \
207 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
208 "scan_dev_for_boot_part=" \
209 "part list ${devtype} ${devnum} devplist; " \
210 "env exists devplist || setenv devplist 1; " \
211 "for distro_bootpart in ${devplist}; do " \
212 "if fstype ${devtype} " \
213 "${devnum}:${distro_bootpart} " \
214 "bootfstype; then " \
215 "run scan_dev_for_boot; " \
218 "scan_dev_for_boot=" \
219 "echo Scanning ${devtype} " \
220 "${devnum}:${distro_bootpart}...; " \
221 "for prefix in ${boot_prefixes}; do " \
222 "run scan_dev_for_scripts; " \
226 "load ${devtype} ${devnum}:${distro_bootpart} " \
227 "${scriptaddr} ${prefix}${script}; " \
228 "env exists secureboot && load ${devtype} " \
229 "${devnum}:${distro_bootpart} " \
230 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
231 "env exists secureboot " \
232 "&& esbc_validate ${scripthdraddr};" \
233 "source ${scriptaddr}\0" \
234 "installer=load mmc 0:2 $load_addr " \
235 "/flex_installer_arm32.itb; " \
236 "bootm $load_addr#ls1021atwr\0" \
237 "qspi_bootcmd=echo Trying load from qspi..;" \
238 "sf probe && sf read $load_addr " \
239 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
240 "nor_bootcmd=echo Trying load from nor..;" \
241 "cp.b $kernel_addr $load_addr " \
242 "$kernel_size && bootm $load_addr#$board\0"
244 #define CONFIG_EXTRA_ENV_SETTINGS \
245 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
246 "cma=64M@0x0-0xb0000000\0" \
247 "initrd_high=0xffffffff\0" \
248 "kernel_addr=0x61000000\0" \
249 "kernelheader_addr=0x60800000\0" \
250 "scriptaddr=0x80000000\0" \
251 "scripthdraddr=0x80080000\0" \
252 "fdtheader_addr_r=0x80100000\0" \
253 "kernelheader_addr_r=0x80200000\0" \
254 "kernel_addr_r=0x81000000\0" \
255 "kernelheader_size=0x40000\0" \
256 "fdt_addr_r=0x90000000\0" \
257 "ramdisk_addr_r=0xa0000000\0" \
258 "load_addr=0xa0000000\0" \
259 "kernel_size=0x2800000\0" \
260 "kernel_addr_sd=0x8000\0" \
261 "kernel_size_sd=0x14000\0" \
262 "kernelhdr_addr_sd=0x4000\0" \
263 "kernelhdr_size_sd=0x10\0" \
264 "othbootargs=cma=64M@0x0-0xb0000000\0" \
266 "boot_scripts=ls1021atwr_boot.scr\0" \
267 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
268 "scan_dev_for_boot_part=" \
269 "part list ${devtype} ${devnum} devplist; " \
270 "env exists devplist || setenv devplist 1; " \
271 "for distro_bootpart in ${devplist}; do " \
272 "if fstype ${devtype} " \
273 "${devnum}:${distro_bootpart} " \
274 "bootfstype; then " \
275 "run scan_dev_for_boot; " \
278 "scan_dev_for_boot=" \
279 "echo Scanning ${devtype} " \
280 "${devnum}:${distro_bootpart}...; " \
281 "for prefix in ${boot_prefixes}; do " \
282 "run scan_dev_for_scripts; " \
286 "load ${devtype} ${devnum}:${distro_bootpart} " \
287 "${scriptaddr} ${prefix}${script}; " \
288 "env exists secureboot && load ${devtype} " \
289 "${devnum}:${distro_bootpart} " \
290 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
291 "&& esbc_validate ${scripthdraddr};" \
292 "source ${scriptaddr}\0" \
293 "qspi_bootcmd=echo Trying load from qspi..;" \
294 "sf probe && sf read $load_addr " \
295 "$kernel_addr $kernel_size; env exists secureboot " \
296 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
297 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
298 "bootm $load_addr#$board\0" \
299 "nor_bootcmd=echo Trying load from nor..;" \
300 "cp.b $kernel_addr $load_addr " \
301 "$kernel_size; env exists secureboot " \
302 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
303 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
304 "bootm $load_addr#$board\0" \
305 "sd_bootcmd=echo Trying load from SD ..;" \
306 "mmcinfo && mmc read $load_addr " \
307 "$kernel_addr_sd $kernel_size_sd && " \
308 "env exists secureboot && mmc read $kernelheader_addr_r " \
309 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
310 " && esbc_validate ${kernelheader_addr_r};" \
311 "bootm $load_addr#$board\0"
315 * Miscellaneous configurable options
317 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
319 #define CONFIG_LS102XA_STREAM_ID
325 #include <asm/fsl_secure_boot.h>