1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_SYS_FSL_CLK
14 #define CONFIG_SKIP_LOWLEVEL_INIT
15 #define CONFIG_DEEP_SLEEP
18 * Size of malloc() pool
20 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
22 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
23 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
25 #define CONFIG_SYS_CLK_FREQ 100000000
27 #define DDR_SDRAM_CFG 0x470c0008
28 #define DDR_CS0_BNDS 0x008000bf
29 #define DDR_CS0_CONFIG 0x80014302
30 #define DDR_TIMING_CFG_0 0x50550004
31 #define DDR_TIMING_CFG_1 0xbcb38c56
32 #define DDR_TIMING_CFG_2 0x0040d120
33 #define DDR_TIMING_CFG_3 0x010e1000
34 #define DDR_TIMING_CFG_4 0x00000001
35 #define DDR_TIMING_CFG_5 0x03401400
36 #define DDR_SDRAM_CFG_2 0x00401010
37 #define DDR_SDRAM_MODE 0x00061c60
38 #define DDR_SDRAM_MODE_2 0x00180000
39 #define DDR_SDRAM_INTERVAL 0x18600618
40 #define DDR_DDR_WRLVL_CNTL 0x8655f605
41 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
42 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
43 #define DDR_DDR_CDR1 0x80040000
44 #define DDR_DDR_CDR2 0x00000001
45 #define DDR_SDRAM_CLK_CNTL 0x02000000
46 #define DDR_DDR_ZQ_CNTL 0x89080600
47 #define DDR_CS0_CONFIG_2 0
48 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
49 #define SDRAM_CFG2_D_INIT 0x00000010
50 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
51 #define SDRAM_CFG2_FRC_SR 0x80000000
52 #define SDRAM_CFG_BI 0x00000001
54 #ifdef CONFIG_RAMBOOT_PBL
55 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
59 #ifdef CONFIG_SD_BOOT_QSPI
60 #define CONFIG_SYS_FSL_PBL_RCW \
61 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
63 #define CONFIG_SYS_FSL_PBL_RCW \
64 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
67 #ifdef CONFIG_NXP_ESBC
69 * HDR would be appended at end of image and copied to DDR along
72 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
73 #endif /* ifdef CONFIG_NXP_ESBC */
75 #define CONFIG_SPL_MAX_SIZE 0x1a000
76 #define CONFIG_SPL_STACK 0x1001d000
77 #define CONFIG_SPL_PAD_TO 0x1c000
79 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
80 CONFIG_SYS_MONITOR_LEN)
81 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
82 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
83 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85 #ifdef CONFIG_U_BOOT_HDR_SIZE
87 * HDR would be appended at end of image and copied to DDR along
88 * with U-Boot image. Here u-boot max. size is 512K. So if binary
89 * size increases then increase this size in case of secure boot as
90 * it uses raw u-boot image instead of fit image.
92 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
94 #define CONFIG_SYS_MONITOR_LEN 0x100000
95 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
98 #define PHYS_SDRAM 0x80000000
99 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
109 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
110 #define CONFIG_FSL_IFC
111 #define CONFIG_SYS_FLASH_BASE 0x60000000
112 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
114 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
115 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
116 CSPR_PORT_SIZE_16 | \
119 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
121 /* NOR Flash Timing Params */
122 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
124 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
125 FTIM0_NOR_TEADC(0x5) | \
126 FTIM0_NOR_TAVDS(0x0) | \
127 FTIM0_NOR_TEAHC(0x5))
128 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
129 FTIM1_NOR_TRAD_NOR(0x1A) | \
130 FTIM1_NOR_TSEQRAD_NOR(0x13))
131 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
132 FTIM2_NOR_TCH(0x4) | \
133 FTIM2_NOR_TWP(0x1c) | \
134 FTIM2_NOR_TWPH(0x0e))
135 #define CONFIG_SYS_NOR_FTIM3 0
137 #define CONFIG_SYS_FLASH_QUIET_TEST
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
145 #define CONFIG_SYS_FLASH_EMPTY_INFO
146 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
148 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
149 #define CONFIG_SYS_WRITE_SWAPPED_DATA
154 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
155 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
157 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
158 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
162 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
163 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
164 CSOR_NOR_NOR_MODE_AVD_NOR | \
167 /* CPLD Timing parameters for IFC GPCM */
168 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
169 FTIM0_GPCM_TEADC(0xf) | \
170 FTIM0_GPCM_TEAHC(0xf))
171 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
172 FTIM1_GPCM_TRAD(0x3f))
173 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
174 FTIM2_GPCM_TCH(0xf) | \
175 FTIM2_GPCM_TWP(0xff))
176 #define CONFIG_SYS_FPGA_FTIM3 0x0
177 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
185 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
186 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
187 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
188 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
189 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
190 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
191 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
192 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
198 #define CONFIG_LPUART_32B_REG
200 #define CONFIG_SYS_NS16550_SERIAL
201 #ifndef CONFIG_DM_SERIAL
202 #define CONFIG_SYS_NS16550_REG_SIZE 1
204 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
212 #ifdef CONFIG_DM_GPIO
213 #ifndef CONFIG_MPC8XXX_GPIO
214 #define CONFIG_MPC8XXX_GPIO
219 #define CONFIG_SYS_I2C_EEPROM_NXID
220 #define CONFIG_SYS_EEPROM_BUS_NUM 1
229 #ifdef CONFIG_VIDEO_FSL_DCU_FB
230 #define CONFIG_VIDEO_LOGO
231 #define CONFIG_VIDEO_BMP_LOGO
233 #define CONFIG_FSL_DCU_SII9022A
234 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
235 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
242 #ifdef CONFIG_TSEC_ENET
243 #define CONFIG_ETHPRIME "ethernet@2d10000"
247 #define CONFIG_PCIE1 /* PCIE controller 1 */
248 #define CONFIG_PCIE2 /* PCIE controller 2 */
251 #define CONFIG_PCI_SCAN_SHOW
254 #define CONFIG_CMDLINE_TAG
256 #define CONFIG_PEN_ADDR_BIG_ENDIAN
257 #define CONFIG_LAYERSCAPE_NS_ACCESS
258 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
259 #define COUNTER_FREQUENCY 12500000
261 #define CONFIG_HWCONFIG
262 #define HWCONFIG_BUFFER_SIZE 256
264 #define CONFIG_FSL_DEVICE_DISABLE
266 #define BOOT_TARGET_DEVICES(func) \
270 #include <config_distro_bootcmd.h>
273 #define CONFIG_EXTRA_ENV_SETTINGS \
274 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
275 "cma=64M@0x0-0xb0000000\0" \
276 "initrd_high=0xffffffff\0" \
277 "fdt_addr=0x64f00000\0" \
278 "kernel_addr=0x65000000\0" \
279 "scriptaddr=0x80000000\0" \
280 "scripthdraddr=0x80080000\0" \
281 "fdtheader_addr_r=0x80100000\0" \
282 "kernelheader_addr_r=0x80200000\0" \
283 "kernel_addr_r=0x81000000\0" \
284 "fdt_addr_r=0x90000000\0" \
285 "ramdisk_addr_r=0xa0000000\0" \
286 "load_addr=0xa0000000\0" \
287 "kernel_size=0x2800000\0" \
288 "kernel_addr_sd=0x8000\0" \
289 "kernel_size_sd=0x14000\0" \
290 "othbootargs=cma=64M@0x0-0xb0000000\0" \
292 "boot_scripts=ls1021atwr_boot.scr\0" \
293 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
294 "scan_dev_for_boot_part=" \
295 "part list ${devtype} ${devnum} devplist; " \
296 "env exists devplist || setenv devplist 1; " \
297 "for distro_bootpart in ${devplist}; do " \
298 "if fstype ${devtype} " \
299 "${devnum}:${distro_bootpart} " \
300 "bootfstype; then " \
301 "run scan_dev_for_boot; " \
304 "scan_dev_for_boot=" \
305 "echo Scanning ${devtype} " \
306 "${devnum}:${distro_bootpart}...; " \
307 "for prefix in ${boot_prefixes}; do " \
308 "run scan_dev_for_scripts; " \
312 "load ${devtype} ${devnum}:${distro_bootpart} " \
313 "${scriptaddr} ${prefix}${script}; " \
314 "env exists secureboot && load ${devtype} " \
315 "${devnum}:${distro_bootpart} " \
316 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
317 "env exists secureboot " \
318 "&& esbc_validate ${scripthdraddr};" \
319 "source ${scriptaddr}\0" \
320 "installer=load mmc 0:2 $load_addr " \
321 "/flex_installer_arm32.itb; " \
322 "bootm $load_addr#ls1021atwr\0" \
323 "qspi_bootcmd=echo Trying load from qspi..;" \
324 "sf probe && sf read $load_addr " \
325 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
326 "nor_bootcmd=echo Trying load from nor..;" \
327 "cp.b $kernel_addr $load_addr " \
328 "$kernel_size && bootm $load_addr#$board\0"
330 #define CONFIG_EXTRA_ENV_SETTINGS \
331 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
332 "cma=64M@0x0-0xb0000000\0" \
333 "initrd_high=0xffffffff\0" \
334 "fdt_addr=0x64f00000\0" \
335 "kernel_addr=0x61000000\0" \
336 "kernelheader_addr=0x60800000\0" \
337 "scriptaddr=0x80000000\0" \
338 "scripthdraddr=0x80080000\0" \
339 "fdtheader_addr_r=0x80100000\0" \
340 "kernelheader_addr_r=0x80200000\0" \
341 "kernel_addr_r=0x81000000\0" \
342 "kernelheader_size=0x40000\0" \
343 "fdt_addr_r=0x90000000\0" \
344 "ramdisk_addr_r=0xa0000000\0" \
345 "load_addr=0xa0000000\0" \
346 "kernel_size=0x2800000\0" \
347 "kernel_addr_sd=0x8000\0" \
348 "kernel_size_sd=0x14000\0" \
349 "kernelhdr_addr_sd=0x4000\0" \
350 "kernelhdr_size_sd=0x10\0" \
351 "othbootargs=cma=64M@0x0-0xb0000000\0" \
353 "boot_scripts=ls1021atwr_boot.scr\0" \
354 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
355 "scan_dev_for_boot_part=" \
356 "part list ${devtype} ${devnum} devplist; " \
357 "env exists devplist || setenv devplist 1; " \
358 "for distro_bootpart in ${devplist}; do " \
359 "if fstype ${devtype} " \
360 "${devnum}:${distro_bootpart} " \
361 "bootfstype; then " \
362 "run scan_dev_for_boot; " \
365 "scan_dev_for_boot=" \
366 "echo Scanning ${devtype} " \
367 "${devnum}:${distro_bootpart}...; " \
368 "for prefix in ${boot_prefixes}; do " \
369 "run scan_dev_for_scripts; " \
373 "load ${devtype} ${devnum}:${distro_bootpart} " \
374 "${scriptaddr} ${prefix}${script}; " \
375 "env exists secureboot && load ${devtype} " \
376 "${devnum}:${distro_bootpart} " \
377 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
378 "&& esbc_validate ${scripthdraddr};" \
379 "source ${scriptaddr}\0" \
380 "qspi_bootcmd=echo Trying load from qspi..;" \
381 "sf probe && sf read $load_addr " \
382 "$kernel_addr $kernel_size; env exists secureboot " \
383 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
384 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
385 "bootm $load_addr#$board\0" \
386 "nor_bootcmd=echo Trying load from nor..;" \
387 "cp.b $kernel_addr $load_addr " \
388 "$kernel_size; env exists secureboot " \
389 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
390 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
391 "bootm $load_addr#$board\0" \
392 "sd_bootcmd=echo Trying load from SD ..;" \
393 "mmcinfo && mmc read $load_addr " \
394 "$kernel_addr_sd $kernel_size_sd && " \
395 "env exists secureboot && mmc read $kernelheader_addr_r " \
396 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
397 " && esbc_validate ${kernelheader_addr_r};" \
398 "bootm $load_addr#$board\0"
401 #undef CONFIG_BOOTCOMMAND
402 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
403 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
404 "env exists secureboot && esbc_halt"
405 #elif defined(CONFIG_SD_BOOT)
406 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
407 "env exists secureboot && esbc_halt;"
409 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
410 "env exists secureboot && esbc_halt;"
414 * Miscellaneous configurable options
416 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
418 #define CONFIG_LS102XA_STREAM_ID
420 #define CONFIG_SYS_INIT_SP_OFFSET \
421 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
422 #define CONFIG_SYS_INIT_SP_ADDR \
423 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
425 #ifdef CONFIG_SPL_BUILD
426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
431 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
437 #include <asm/fsl_secure_boot.h>
438 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */