1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_SYS_FSL_CLK
14 #define CONFIG_DEEP_SLEEP
16 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
17 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
19 #define CONFIG_SYS_CLK_FREQ 100000000
21 #define DDR_SDRAM_CFG 0x470c0008
22 #define DDR_CS0_BNDS 0x008000bf
23 #define DDR_CS0_CONFIG 0x80014302
24 #define DDR_TIMING_CFG_0 0x50550004
25 #define DDR_TIMING_CFG_1 0xbcb38c56
26 #define DDR_TIMING_CFG_2 0x0040d120
27 #define DDR_TIMING_CFG_3 0x010e1000
28 #define DDR_TIMING_CFG_4 0x00000001
29 #define DDR_TIMING_CFG_5 0x03401400
30 #define DDR_SDRAM_CFG_2 0x00401010
31 #define DDR_SDRAM_MODE 0x00061c60
32 #define DDR_SDRAM_MODE_2 0x00180000
33 #define DDR_SDRAM_INTERVAL 0x18600618
34 #define DDR_DDR_WRLVL_CNTL 0x8655f605
35 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
36 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
37 #define DDR_DDR_CDR1 0x80040000
38 #define DDR_DDR_CDR2 0x00000001
39 #define DDR_SDRAM_CLK_CNTL 0x02000000
40 #define DDR_DDR_ZQ_CNTL 0x89080600
41 #define DDR_CS0_CONFIG_2 0
42 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
43 #define SDRAM_CFG2_D_INIT 0x00000010
44 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
45 #define SDRAM_CFG2_FRC_SR 0x80000000
46 #define SDRAM_CFG_BI 0x00000001
49 #ifdef CONFIG_NXP_ESBC
51 * HDR would be appended at end of image and copied to DDR along
54 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
55 #endif /* ifdef CONFIG_NXP_ESBC */
57 #define CONFIG_SPL_MAX_SIZE 0x1a000
58 #define CONFIG_SPL_STACK 0x1001d000
59 #define CONFIG_SPL_PAD_TO 0x1c000
61 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
62 CONFIG_SYS_MONITOR_LEN)
63 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
64 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
65 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
67 #ifdef CONFIG_U_BOOT_HDR_SIZE
69 * HDR would be appended at end of image and copied to DDR along
70 * with U-Boot image. Here u-boot max. size is 512K. So if binary
71 * size increases then increase this size in case of secure boot as
72 * it uses raw u-boot image instead of fit image.
74 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
76 #define CONFIG_SYS_MONITOR_LEN 0x100000
77 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
80 #define PHYS_SDRAM 0x80000000
81 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
86 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
91 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
92 #define CONFIG_SYS_FLASH_BASE 0x60000000
93 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
95 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
96 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
100 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
102 /* NOR Flash Timing Params */
103 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
105 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
106 FTIM0_NOR_TEADC(0x5) | \
107 FTIM0_NOR_TAVDS(0x0) | \
108 FTIM0_NOR_TEAHC(0x5))
109 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
110 FTIM1_NOR_TRAD_NOR(0x1A) | \
111 FTIM1_NOR_TSEQRAD_NOR(0x13))
112 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
113 FTIM2_NOR_TCH(0x4) | \
114 FTIM2_NOR_TWP(0x1c) | \
115 FTIM2_NOR_TWPH(0x0e))
116 #define CONFIG_SYS_NOR_FTIM3 0
118 #define CONFIG_SYS_FLASH_QUIET_TEST
119 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
122 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
123 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
124 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
126 #define CONFIG_SYS_FLASH_EMPTY_INFO
127 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
129 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
130 #define CONFIG_SYS_WRITE_SWAPPED_DATA
135 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
136 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
138 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
139 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
143 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
144 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
145 CSOR_NOR_NOR_MODE_AVD_NOR | \
148 /* CPLD Timing parameters for IFC GPCM */
149 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
150 FTIM0_GPCM_TEADC(0xf) | \
151 FTIM0_GPCM_TEAHC(0xf))
152 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
153 FTIM1_GPCM_TRAD(0x3f))
154 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
155 FTIM2_GPCM_TCH(0xf) | \
156 FTIM2_GPCM_TWP(0xff))
157 #define CONFIG_SYS_FPGA_FTIM3 0x0
158 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
159 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
160 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
161 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
162 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
163 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
164 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
165 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
166 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
167 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
168 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
169 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
170 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
171 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
172 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
173 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
179 #define CONFIG_LPUART_32B_REG
181 #define CONFIG_SYS_NS16550_SERIAL
182 #ifndef CONFIG_DM_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE 1
185 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
195 #define CONFIG_SYS_I2C_EEPROM_NXID
196 #define CONFIG_SYS_EEPROM_BUS_NUM 1
205 #ifdef CONFIG_VIDEO_FSL_DCU_FB
206 #define CONFIG_VIDEO_LOGO
207 #define CONFIG_VIDEO_BMP_LOGO
209 #define CONFIG_FSL_DCU_SII9022A
210 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
211 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
218 #ifdef CONFIG_TSEC_ENET
219 #define CONFIG_ETHPRIME "ethernet@2d10000"
223 #define CONFIG_PCIE1 /* PCIE controller 1 */
224 #define CONFIG_PCIE2 /* PCIE controller 2 */
227 #define CONFIG_PCI_SCAN_SHOW
230 #define CONFIG_PEN_ADDR_BIG_ENDIAN
231 #define CONFIG_LAYERSCAPE_NS_ACCESS
232 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
233 #define COUNTER_FREQUENCY 12500000
235 #define CONFIG_HWCONFIG
236 #define HWCONFIG_BUFFER_SIZE 256
238 #define CONFIG_FSL_DEVICE_DISABLE
240 #define BOOT_TARGET_DEVICES(func) \
244 #include <config_distro_bootcmd.h>
247 #define CONFIG_EXTRA_ENV_SETTINGS \
248 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
249 "cma=64M@0x0-0xb0000000\0" \
250 "initrd_high=0xffffffff\0" \
251 "fdt_addr=0x64f00000\0" \
252 "kernel_addr=0x65000000\0" \
253 "scriptaddr=0x80000000\0" \
254 "scripthdraddr=0x80080000\0" \
255 "fdtheader_addr_r=0x80100000\0" \
256 "kernelheader_addr_r=0x80200000\0" \
257 "kernel_addr_r=0x81000000\0" \
258 "fdt_addr_r=0x90000000\0" \
259 "ramdisk_addr_r=0xa0000000\0" \
260 "load_addr=0xa0000000\0" \
261 "kernel_size=0x2800000\0" \
262 "kernel_addr_sd=0x8000\0" \
263 "kernel_size_sd=0x14000\0" \
264 "othbootargs=cma=64M@0x0-0xb0000000\0" \
266 "boot_scripts=ls1021atwr_boot.scr\0" \
267 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
268 "scan_dev_for_boot_part=" \
269 "part list ${devtype} ${devnum} devplist; " \
270 "env exists devplist || setenv devplist 1; " \
271 "for distro_bootpart in ${devplist}; do " \
272 "if fstype ${devtype} " \
273 "${devnum}:${distro_bootpart} " \
274 "bootfstype; then " \
275 "run scan_dev_for_boot; " \
278 "scan_dev_for_boot=" \
279 "echo Scanning ${devtype} " \
280 "${devnum}:${distro_bootpart}...; " \
281 "for prefix in ${boot_prefixes}; do " \
282 "run scan_dev_for_scripts; " \
286 "load ${devtype} ${devnum}:${distro_bootpart} " \
287 "${scriptaddr} ${prefix}${script}; " \
288 "env exists secureboot && load ${devtype} " \
289 "${devnum}:${distro_bootpart} " \
290 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
291 "env exists secureboot " \
292 "&& esbc_validate ${scripthdraddr};" \
293 "source ${scriptaddr}\0" \
294 "installer=load mmc 0:2 $load_addr " \
295 "/flex_installer_arm32.itb; " \
296 "bootm $load_addr#ls1021atwr\0" \
297 "qspi_bootcmd=echo Trying load from qspi..;" \
298 "sf probe && sf read $load_addr " \
299 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
300 "nor_bootcmd=echo Trying load from nor..;" \
301 "cp.b $kernel_addr $load_addr " \
302 "$kernel_size && bootm $load_addr#$board\0"
304 #define CONFIG_EXTRA_ENV_SETTINGS \
305 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
306 "cma=64M@0x0-0xb0000000\0" \
307 "initrd_high=0xffffffff\0" \
308 "fdt_addr=0x64f00000\0" \
309 "kernel_addr=0x61000000\0" \
310 "kernelheader_addr=0x60800000\0" \
311 "scriptaddr=0x80000000\0" \
312 "scripthdraddr=0x80080000\0" \
313 "fdtheader_addr_r=0x80100000\0" \
314 "kernelheader_addr_r=0x80200000\0" \
315 "kernel_addr_r=0x81000000\0" \
316 "kernelheader_size=0x40000\0" \
317 "fdt_addr_r=0x90000000\0" \
318 "ramdisk_addr_r=0xa0000000\0" \
319 "load_addr=0xa0000000\0" \
320 "kernel_size=0x2800000\0" \
321 "kernel_addr_sd=0x8000\0" \
322 "kernel_size_sd=0x14000\0" \
323 "kernelhdr_addr_sd=0x4000\0" \
324 "kernelhdr_size_sd=0x10\0" \
325 "othbootargs=cma=64M@0x0-0xb0000000\0" \
327 "boot_scripts=ls1021atwr_boot.scr\0" \
328 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
329 "scan_dev_for_boot_part=" \
330 "part list ${devtype} ${devnum} devplist; " \
331 "env exists devplist || setenv devplist 1; " \
332 "for distro_bootpart in ${devplist}; do " \
333 "if fstype ${devtype} " \
334 "${devnum}:${distro_bootpart} " \
335 "bootfstype; then " \
336 "run scan_dev_for_boot; " \
339 "scan_dev_for_boot=" \
340 "echo Scanning ${devtype} " \
341 "${devnum}:${distro_bootpart}...; " \
342 "for prefix in ${boot_prefixes}; do " \
343 "run scan_dev_for_scripts; " \
347 "load ${devtype} ${devnum}:${distro_bootpart} " \
348 "${scriptaddr} ${prefix}${script}; " \
349 "env exists secureboot && load ${devtype} " \
350 "${devnum}:${distro_bootpart} " \
351 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
352 "&& esbc_validate ${scripthdraddr};" \
353 "source ${scriptaddr}\0" \
354 "qspi_bootcmd=echo Trying load from qspi..;" \
355 "sf probe && sf read $load_addr " \
356 "$kernel_addr $kernel_size; env exists secureboot " \
357 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
358 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
359 "bootm $load_addr#$board\0" \
360 "nor_bootcmd=echo Trying load from nor..;" \
361 "cp.b $kernel_addr $load_addr " \
362 "$kernel_size; env exists secureboot " \
363 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
364 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
365 "bootm $load_addr#$board\0" \
366 "sd_bootcmd=echo Trying load from SD ..;" \
367 "mmcinfo && mmc read $load_addr " \
368 "$kernel_addr_sd $kernel_size_sd && " \
369 "env exists secureboot && mmc read $kernelheader_addr_r " \
370 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
371 " && esbc_validate ${kernelheader_addr_r};" \
372 "bootm $load_addr#$board\0"
376 * Miscellaneous configurable options
378 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
380 #define CONFIG_LS102XA_STREAM_ID
382 #define CONFIG_SYS_INIT_SP_OFFSET \
383 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
384 #define CONFIG_SYS_INIT_SP_ADDR \
385 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
387 #ifdef CONFIG_SPL_BUILD
388 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
390 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
397 #include <asm/fsl_secure_boot.h>
398 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */