include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #define DDR_SDRAM_CFG                   0x470c0008
  14 #define DDR_CS0_BNDS                    0x008000bf
  15 #define DDR_CS0_CONFIG                  0x80014302
  16 #define DDR_TIMING_CFG_0                0x50550004
  17 #define DDR_TIMING_CFG_1                0xbcb38c56
  18 #define DDR_TIMING_CFG_2                0x0040d120
  19 #define DDR_TIMING_CFG_3                0x010e1000
  20 #define DDR_TIMING_CFG_4                0x00000001
  21 #define DDR_TIMING_CFG_5                0x03401400
  22 #define DDR_SDRAM_CFG_2                 0x00401010
  23 #define DDR_SDRAM_MODE                  0x00061c60
  24 #define DDR_SDRAM_MODE_2                0x00180000
  25 #define DDR_SDRAM_INTERVAL              0x18600618
  26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  29 #define DDR_DDR_CDR1                    0x80040000
  30 #define DDR_DDR_CDR2                    0x00000001
  31 #define DDR_SDRAM_CLK_CNTL              0x02000000
  32 #define DDR_DDR_ZQ_CNTL                 0x89080600
  33 #define DDR_CS0_CONFIG_2                0
  34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  35 #define SDRAM_CFG2_D_INIT               0x00000010
  36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  37 #define SDRAM_CFG2_FRC_SR               0x80000000
  38 #define SDRAM_CFG_BI                    0x00000001
  39
  40 #ifdef CONFIG_SD_BOOT
  41 #ifdef CONFIG_NXP_ESBC
  42 /*
  43  * HDR would be appended at end of image and copied to DDR along
  44  * with U-Boot image.
  45  */
  46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  47 #endif /* ifdef CONFIG_NXP_ESBC */
  48
  49 #define CONFIG_SPL_MAX_SIZE             0x1a000
  50 #define CONFIG_SPL_STACK                0x1001d000
  51 #define CONFIG_SPL_PAD_TO               0x1c000
  52
  53 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  54                 CONFIG_SYS_MONITOR_LEN)
  55 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  56 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  57 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  58
  59 #ifdef CONFIG_U_BOOT_HDR_SIZE
  60 /*
  61  * HDR would be appended at end of image and copied to DDR along
  62  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  63  * size increases then increase this size in case of secure boot as
  64  * it uses raw u-boot image instead of fit image.
  65  */
  66 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  67 #else
  68 #define CONFIG_SYS_MONITOR_LEN          0x100000
  69 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  70 #endif
  71
  72 #define PHYS_SDRAM                      0x80000000
  73 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  74
  75 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  76 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  77
  78 /*
  79  * IFC Definitions
  80  */
  81 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  82 #define CONFIG_SYS_FLASH_BASE           0x60000000
  83 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  84
  85 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  86 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  87                                 CSPR_PORT_SIZE_16 | \
  88                                 CSPR_MSEL_NOR | \
  89                                 CSPR_V)
  90 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  91
  92 /* NOR Flash Timing Params */
  93 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  94                                         CSOR_NOR_TRHZ_80)
  95 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  96                                         FTIM0_NOR_TEADC(0x5) | \
  97                                         FTIM0_NOR_TAVDS(0x0) | \
  98                                         FTIM0_NOR_TEAHC(0x5))
  99 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 100                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 101                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 102 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 103                                         FTIM2_NOR_TCH(0x4) | \
 104                                         FTIM2_NOR_TWP(0x1c) | \
 105                                         FTIM2_NOR_TWPH(0x0e))
 106 #define CONFIG_SYS_NOR_FTIM3            0
 107
 108 #define CONFIG_SYS_FLASH_QUIET_TEST
 109 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 110
 111 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 114
 115 #define CONFIG_SYS_FLASH_EMPTY_INFO
 116 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 117
 118 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 119 #endif
 120
 121 /* CPLD */
 122
 123 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 124 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 125
 126 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 127 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 128                                         CSPR_PORT_SIZE_8 | \
 129                                         CSPR_MSEL_GPCM | \
 130                                         CSPR_V)
 131 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 132 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 133                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 134                                         CSOR_NOR_TRHZ_80)
 135
 136 /* CPLD Timing parameters for IFC GPCM */
 137 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 138                                         FTIM0_GPCM_TEADC(0xf) | \
 139                                         FTIM0_GPCM_TEAHC(0xf))
 140 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 141                                         FTIM1_GPCM_TRAD(0x3f))
 142 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 143                                         FTIM2_GPCM_TCH(0xf) | \
 144                                         FTIM2_GPCM_TWP(0xff))
 145 #define CONFIG_SYS_FPGA_FTIM3           0x0
 146 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 147 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 148 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 149 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 150 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 151 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 152 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 153 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 154 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 155 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 156 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 157 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 158 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 159 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 160 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 161 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 162
 163 /*
 164  * Serial Port
 165  */
 166 #ifndef CONFIG_LPUART
 167 #define CONFIG_SYS_NS16550_SERIAL
 168 #ifndef CONFIG_DM_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #endif
 171 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 172 #endif
 173
 174 /*
 175  * I2C
 176  */
 177
 178 /* GPIO */
 179
 180 /* EEPROM */
 181 #define CONFIG_SYS_I2C_EEPROM_NXID
 182 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 183
 184 /* PCIe */
 185 #define CONFIG_PCIE1            /* PCIE controller 1 */
 186 #define CONFIG_PCIE2            /* PCIE controller 2 */
 187
 188 #ifdef CONFIG_PCI
 189 #define CONFIG_PCI_SCAN_SHOW
 190 #endif
 191
 192 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 193 #define CONFIG_LAYERSCAPE_NS_ACCESS
 194 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 195 #define COUNTER_FREQUENCY               12500000
 196
 197 #define CONFIG_HWCONFIG
 198 #define HWCONFIG_BUFFER_SIZE            256
 199
 200 #define CONFIG_FSL_DEVICE_DISABLE
 201
 202 #define BOOT_TARGET_DEVICES(func) \
 203         func(MMC, mmc, 0) \
 204         func(USB, usb, 0) \
 205         func(DHCP, dhcp, na)
 206 #include <config_distro_bootcmd.h>
 207
 208 #ifdef CONFIG_LPUART
 209 #define CONFIG_EXTRA_ENV_SETTINGS       \
 210         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 211                 "cma=64M@0x0-0xb0000000\0" \
 212         "initrd_high=0xffffffff\0"      \
 213         "fdt_addr=0x64f00000\0"         \
 214         "kernel_addr=0x65000000\0"      \
 215         "scriptaddr=0x80000000\0"       \
 216         "scripthdraddr=0x80080000\0"    \
 217         "fdtheader_addr_r=0x80100000\0" \
 218         "kernelheader_addr_r=0x80200000\0"      \
 219         "kernel_addr_r=0x81000000\0"    \
 220         "fdt_addr_r=0x90000000\0"       \
 221         "ramdisk_addr_r=0xa0000000\0"   \
 222         "load_addr=0xa0000000\0"        \
 223         "kernel_size=0x2800000\0"       \
 224         "kernel_addr_sd=0x8000\0"       \
 225         "kernel_size_sd=0x14000\0"      \
 226         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 227         BOOTENV                         \
 228         "boot_scripts=ls1021atwr_boot.scr\0"    \
 229         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 230                 "scan_dev_for_boot_part="       \
 231                         "part list ${devtype} ${devnum} devplist; "     \
 232                         "env exists devplist || setenv devplist 1; "    \
 233                         "for distro_bootpart in ${devplist}; do "       \
 234                         "if fstype ${devtype} "                         \
 235                                 "${devnum}:${distro_bootpart} "         \
 236                                 "bootfstype; then "                     \
 237                                 "run scan_dev_for_boot; "               \
 238                         "fi; "                  \
 239                 "done\0"                        \
 240         "scan_dev_for_boot="                              \
 241                 "echo Scanning ${devtype} "               \
 242                                 "${devnum}:${distro_bootpart}...; "  \
 243                 "for prefix in ${boot_prefixes}; do "     \
 244                         "run scan_dev_for_scripts; "      \
 245                 "done;"                                   \
 246                 "\0"                                      \
 247         "boot_a_script="                                  \
 248                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 249                         "${scriptaddr} ${prefix}${script}; "    \
 250                 "env exists secureboot && load ${devtype} "     \
 251                         "${devnum}:${distro_bootpart} "         \
 252                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 253                         "env exists secureboot "        \
 254                         "&& esbc_validate ${scripthdraddr};"    \
 255                 "source ${scriptaddr}\0"          \
 256         "installer=load mmc 0:2 $load_addr "    \
 257                 "/flex_installer_arm32.itb; "           \
 258                 "bootm $load_addr#ls1021atwr\0" \
 259         "qspi_bootcmd=echo Trying load from qspi..;"    \
 260                 "sf probe && sf read $load_addr "       \
 261                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 262         "nor_bootcmd=echo Trying load from nor..;"      \
 263                 "cp.b $kernel_addr $load_addr "         \
 264                 "$kernel_size && bootm $load_addr#$board\0"
 265 #else
 266 #define CONFIG_EXTRA_ENV_SETTINGS       \
 267         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 268                 "cma=64M@0x0-0xb0000000\0" \
 269         "initrd_high=0xffffffff\0"      \
 270         "fdt_addr=0x64f00000\0"         \
 271         "kernel_addr=0x61000000\0"      \
 272         "kernelheader_addr=0x60800000\0"        \
 273         "scriptaddr=0x80000000\0"       \
 274         "scripthdraddr=0x80080000\0"    \
 275         "fdtheader_addr_r=0x80100000\0" \
 276         "kernelheader_addr_r=0x80200000\0"      \
 277         "kernel_addr_r=0x81000000\0"    \
 278         "kernelheader_size=0x40000\0"   \
 279         "fdt_addr_r=0x90000000\0"       \
 280         "ramdisk_addr_r=0xa0000000\0"   \
 281         "load_addr=0xa0000000\0"        \
 282         "kernel_size=0x2800000\0"       \
 283         "kernel_addr_sd=0x8000\0"       \
 284         "kernel_size_sd=0x14000\0"      \
 285         "kernelhdr_addr_sd=0x4000\0"            \
 286         "kernelhdr_size_sd=0x10\0"              \
 287         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 288         BOOTENV                         \
 289         "boot_scripts=ls1021atwr_boot.scr\0"    \
 290         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 291                 "scan_dev_for_boot_part="       \
 292                         "part list ${devtype} ${devnum} devplist; "     \
 293                         "env exists devplist || setenv devplist 1; "    \
 294                         "for distro_bootpart in ${devplist}; do "       \
 295                         "if fstype ${devtype} "                         \
 296                                 "${devnum}:${distro_bootpart} "         \
 297                                 "bootfstype; then "                     \
 298                                 "run scan_dev_for_boot; "               \
 299                         "fi; "                  \
 300                 "done\0"                        \
 301         "scan_dev_for_boot="                              \
 302                 "echo Scanning ${devtype} "               \
 303                                 "${devnum}:${distro_bootpart}...; "  \
 304                 "for prefix in ${boot_prefixes}; do "     \
 305                         "run scan_dev_for_scripts; "      \
 306                 "done;"                                   \
 307                 "\0"                                      \
 308         "boot_a_script="                                  \
 309                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 310                         "${scriptaddr} ${prefix}${script}; "    \
 311                 "env exists secureboot && load ${devtype} "     \
 312                         "${devnum}:${distro_bootpart} "         \
 313                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 314                         "&& esbc_validate ${scripthdraddr};"    \
 315                 "source ${scriptaddr}\0"          \
 316         "qspi_bootcmd=echo Trying load from qspi..;"    \
 317                 "sf probe && sf read $load_addr "       \
 318                 "$kernel_addr $kernel_size; env exists secureboot "     \
 319                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 320                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 321                 "bootm $load_addr#$board\0" \
 322         "nor_bootcmd=echo Trying load from nor..;"      \
 323                 "cp.b $kernel_addr $load_addr "         \
 324                 "$kernel_size; env exists secureboot "  \
 325                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 326                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 327                 "bootm $load_addr#$board\0"     \
 328         "sd_bootcmd=echo Trying load from SD ..;"       \
 329                 "mmcinfo && mmc read $load_addr "       \
 330                 "$kernel_addr_sd $kernel_size_sd && "   \
 331                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 332                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 333                 " && esbc_validate ${kernelheader_addr_r};"     \
 334                 "bootm $load_addr#$board\0"
 335 #endif
 336
 337 /*
 338  * Miscellaneous configurable options
 339  */
 340 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 341
 342 #define CONFIG_LS102XA_STREAM_ID
 343
 344 #define CONFIG_SYS_INIT_SP_OFFSET \
 345         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 346 #define CONFIG_SYS_INIT_SP_ADDR \
 347         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 348
 349 /*
 350  * Environment
 351  */
 352
 353 #include <asm/fsl_secure_boot.h>
 354 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 355
 356 #endif