2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI
13 #define CONFIG_ARMV7_PSCI_1_0
14 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
21 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #define CONFIG_BOARD_EARLY_INIT_F
23 #define CONFIG_DEEP_SLEEP
24 #ifdef CONFIG_DEEP_SLEEP
25 #define CONFIG_SILENT_CONSOLE
29 * Size of malloc() pool
31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
41 * EHCI Support - disbaled by default as
42 * there is no signal coming out of soc on
43 * this board for this controller. However,
44 * the silicon still has this controller,
45 * and anyone can use this controller by
46 * taking signals out on their board.
49 /*#define CONFIG_HAS_FSL_DR_USB*/
51 #ifdef CONFIG_HAS_FSL_DR_USB
52 #define CONFIG_USB_EHCI
53 #define CONFIG_USB_EHCI_FSL
54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
57 /* XHCI Support - enabled by default */
58 #define CONFIG_HAS_FSL_XHCI_USB
60 #ifdef CONFIG_HAS_FSL_XHCI_USB
61 #define CONFIG_USB_XHCI_FSL
62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
66 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
67 #define CONFIG_USB_STORAGE
71 * Generic Timer Definitions
73 #define GENERIC_TIMER_CLK 12500000
75 #define CONFIG_SYS_CLK_FREQ 100000000
76 #define CONFIG_DDR_CLK_FREQ 100000000
78 #define DDR_SDRAM_CFG 0x470c0008
79 #define DDR_CS0_BNDS 0x008000bf
80 #define DDR_CS0_CONFIG 0x80014302
81 #define DDR_TIMING_CFG_0 0x50550004
82 #define DDR_TIMING_CFG_1 0xbcb38c56
83 #define DDR_TIMING_CFG_2 0x0040d120
84 #define DDR_TIMING_CFG_3 0x010e1000
85 #define DDR_TIMING_CFG_4 0x00000001
86 #define DDR_TIMING_CFG_5 0x03401400
87 #define DDR_SDRAM_CFG_2 0x00401010
88 #define DDR_SDRAM_MODE 0x00061c60
89 #define DDR_SDRAM_MODE_2 0x00180000
90 #define DDR_SDRAM_INTERVAL 0x18600618
91 #define DDR_DDR_WRLVL_CNTL 0x8655f605
92 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
93 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
94 #define DDR_DDR_CDR1 0x80040000
95 #define DDR_DDR_CDR2 0x00000001
96 #define DDR_SDRAM_CLK_CNTL 0x02000000
97 #define DDR_DDR_ZQ_CNTL 0x89080600
98 #define DDR_CS0_CONFIG_2 0
99 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
100 #define SDRAM_CFG2_D_INIT 0x00000010
101 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
102 #define SDRAM_CFG2_FRC_SR 0x80000000
103 #define SDRAM_CFG_BI 0x00000001
105 #ifdef CONFIG_RAMBOOT_PBL
106 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
109 #ifdef CONFIG_SD_BOOT
110 #ifdef CONFIG_SD_BOOT_QSPI
111 #define CONFIG_SYS_FSL_PBL_RCW \
112 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
114 #define CONFIG_SYS_FSL_PBL_RCW \
115 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
117 #define CONFIG_SPL_FRAMEWORK
118 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
119 #define CONFIG_SPL_LIBCOMMON_SUPPORT
120 #define CONFIG_SPL_LIBGENERIC_SUPPORT
121 #define CONFIG_SPL_ENV_SUPPORT
122 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
123 #define CONFIG_SPL_I2C_SUPPORT
124 #define CONFIG_SPL_WATCHDOG_SUPPORT
125 #define CONFIG_SPL_SERIAL_SUPPORT
126 #define CONFIG_SPL_MMC_SUPPORT
127 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
129 #ifdef CONFIG_SECURE_BOOT
130 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
132 * HDR would be appended at end of image and copied to DDR along
135 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
136 (CONFIG_U_BOOT_HDR_SIZE / 512)
138 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
139 #endif /* ifdef CONFIG_SECURE_BOOT */
141 #define CONFIG_SPL_TEXT_BASE 0x10000000
142 #define CONFIG_SPL_MAX_SIZE 0x1a000
143 #define CONFIG_SPL_STACK 0x1001d000
144 #define CONFIG_SPL_PAD_TO 0x1c000
145 #define CONFIG_SYS_TEXT_BASE 0x82000000
147 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
148 CONFIG_SYS_MONITOR_LEN)
149 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
150 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
151 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
153 #ifdef CONFIG_U_BOOT_HDR_SIZE
155 * HDR would be appended at end of image and copied to DDR along
156 * with U-Boot image. Here u-boot max. size is 512K. So if binary
157 * size increases then increase this size in case of secure boot as
158 * it uses raw u-boot image instead of fit image.
160 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
162 #define CONFIG_SYS_MONITOR_LEN 0x80000
163 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
166 #ifdef CONFIG_QSPI_BOOT
167 #define CONFIG_SYS_TEXT_BASE 0x40010000
170 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
171 #define CONFIG_SYS_NO_FLASH
174 #ifndef CONFIG_SYS_TEXT_BASE
175 #define CONFIG_SYS_TEXT_BASE 0x60100000
178 #define CONFIG_NR_DRAM_BANKS 1
179 #define PHYS_SDRAM 0x80000000
180 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
182 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
183 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
185 #define CONFIG_SYS_HAS_SERDES
187 #define CONFIG_FSL_CAAM /* Enable CAAM */
189 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
190 !defined(CONFIG_QSPI_BOOT)
197 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
198 #define CONFIG_FSL_IFC
199 #define CONFIG_SYS_FLASH_BASE 0x60000000
200 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
202 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
203 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
204 CSPR_PORT_SIZE_16 | \
207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
209 /* NOR Flash Timing Params */
210 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
212 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
213 FTIM0_NOR_TEADC(0x5) | \
214 FTIM0_NOR_TAVDS(0x0) | \
215 FTIM0_NOR_TEAHC(0x5))
216 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
217 FTIM1_NOR_TRAD_NOR(0x1A) | \
218 FTIM1_NOR_TSEQRAD_NOR(0x13))
219 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
220 FTIM2_NOR_TCH(0x4) | \
221 FTIM2_NOR_TWP(0x1c) | \
222 FTIM2_NOR_TWPH(0x0e))
223 #define CONFIG_SYS_NOR_FTIM3 0
225 #define CONFIG_FLASH_CFI_DRIVER
226 #define CONFIG_SYS_FLASH_CFI
227 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
228 #define CONFIG_SYS_FLASH_QUIET_TEST
229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
236 #define CONFIG_SYS_FLASH_EMPTY_INFO
237 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
239 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
240 #define CONFIG_SYS_WRITE_SWAPPED_DATA
245 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
246 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
248 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
249 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
253 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
254 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
255 CSOR_NOR_NOR_MODE_AVD_NOR | \
258 /* CPLD Timing parameters for IFC GPCM */
259 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
260 FTIM0_GPCM_TEADC(0xf) | \
261 FTIM0_GPCM_TEAHC(0xf))
262 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
263 FTIM1_GPCM_TRAD(0x3f))
264 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
265 FTIM2_GPCM_TCH(0xf) | \
266 FTIM2_GPCM_TWP(0xff))
267 #define CONFIG_SYS_FPGA_FTIM3 0x0
268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
270 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
271 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
272 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
273 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
274 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
275 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
276 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
277 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
278 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
279 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
280 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
281 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
282 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
283 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
289 #define CONFIG_LPUART_32B_REG
291 #define CONFIG_CONS_INDEX 1
292 #define CONFIG_SYS_NS16550_SERIAL
293 #ifndef CONFIG_DM_SERIAL
294 #define CONFIG_SYS_NS16550_REG_SIZE 1
296 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
299 #define CONFIG_BAUDRATE 115200
304 #define CONFIG_SYS_I2C
305 #define CONFIG_SYS_I2C_MXC
306 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
307 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
308 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
311 #define CONFIG_ID_EEPROM
312 #define CONFIG_SYS_I2C_EEPROM_NXID
313 #define CONFIG_SYS_EEPROM_BUS_NUM 1
314 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
323 #define CONFIG_FSL_ESDHC
324 #define CONFIG_GENERIC_MMC
326 #define CONFIG_DOS_PARTITION
329 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
331 #define QSPI0_AMBA_BASE 0x40000000
332 #define FSL_QSPI_FLASH_SIZE (1 << 24)
333 #define FSL_QSPI_FLASH_NUM 2
339 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
340 #define CONFIG_DM_SPI_FLASH
346 #define CONFIG_FSL_DCU_FB
348 #ifdef CONFIG_FSL_DCU_FB
350 #define CONFIG_CMD_BMP
351 #define CONFIG_CFB_CONSOLE
352 #define CONFIG_VGA_AS_SINGLE_DEVICE
353 #define CONFIG_VIDEO_LOGO
354 #define CONFIG_VIDEO_BMP_LOGO
355 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
357 #define CONFIG_FSL_DCU_SII9022A
358 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
359 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
365 #define CONFIG_TSEC_ENET
367 #ifdef CONFIG_TSEC_ENET
369 #define CONFIG_MII_DEFAULT_TSEC 1
370 #define CONFIG_TSEC1 1
371 #define CONFIG_TSEC1_NAME "eTSEC1"
372 #define CONFIG_TSEC2 1
373 #define CONFIG_TSEC2_NAME "eTSEC2"
374 #define CONFIG_TSEC3 1
375 #define CONFIG_TSEC3_NAME "eTSEC3"
377 #define TSEC1_PHY_ADDR 2
378 #define TSEC2_PHY_ADDR 0
379 #define TSEC3_PHY_ADDR 1
381 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
382 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
383 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
385 #define TSEC1_PHYIDX 0
386 #define TSEC2_PHYIDX 0
387 #define TSEC3_PHYIDX 0
389 #define CONFIG_ETHPRIME "eTSEC1"
391 #define CONFIG_PHY_GIGE
392 #define CONFIG_PHYLIB
393 #define CONFIG_PHY_ATHEROS
395 #define CONFIG_HAS_ETH0
396 #define CONFIG_HAS_ETH1
397 #define CONFIG_HAS_ETH2
401 #define CONFIG_PCI /* Enable PCI/PCIE */
402 #define CONFIG_PCIE1 /* PCIE controller 1 */
403 #define CONFIG_PCIE2 /* PCIE controller 2 */
404 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
405 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
407 #define CONFIG_SYS_PCI_64BIT
409 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
410 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
411 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
412 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
414 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
415 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
416 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
418 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
419 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
420 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
423 #define CONFIG_PCI_PNP
424 #define CONFIG_PCI_SCAN_SHOW
425 #define CONFIG_CMD_PCI
428 #define CONFIG_CMDLINE_TAG
429 #define CONFIG_CMDLINE_EDITING
431 #define CONFIG_ARMV7_NONSEC
432 #define CONFIG_ARMV7_VIRT
433 #define CONFIG_PEN_ADDR_BIG_ENDIAN
434 #define CONFIG_LAYERSCAPE_NS_ACCESS
435 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
436 #define CONFIG_TIMER_CLK_FREQ 12500000
438 #define CONFIG_HWCONFIG
439 #define HWCONFIG_BUFFER_SIZE 256
441 #define CONFIG_FSL_DEVICE_DISABLE
445 #define CONFIG_EXTRA_ENV_SETTINGS \
446 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
447 "initrd_high=0xffffffff\0" \
448 "fdt_high=0xffffffff\0"
450 #define CONFIG_EXTRA_ENV_SETTINGS \
451 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
452 "initrd_high=0xffffffff\0" \
453 "fdt_high=0xffffffff\0"
457 * Miscellaneous configurable options
459 #define CONFIG_SYS_LONGHELP /* undef to save memory */
460 #define CONFIG_AUTO_COMPLETE
461 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
462 #define CONFIG_SYS_PBSIZE \
463 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
464 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
465 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
467 #define CONFIG_SYS_MEMTEST_START 0x80000000
468 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
470 #define CONFIG_SYS_LOAD_ADDR 0x82000000
472 #define CONFIG_LS102XA_STREAM_ID
476 * The stack sizes are set up in start.S using the settings below
478 #define CONFIG_STACKSIZE (30 * 1024)
480 #define CONFIG_SYS_INIT_SP_OFFSET \
481 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
482 #define CONFIG_SYS_INIT_SP_ADDR \
483 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
485 #ifdef CONFIG_SPL_BUILD
486 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
488 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
491 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
496 #define CONFIG_ENV_OVERWRITE
498 #if defined(CONFIG_SD_BOOT)
499 #define CONFIG_ENV_OFFSET 0x100000
500 #define CONFIG_ENV_IS_IN_MMC
501 #define CONFIG_SYS_MMC_ENV_DEV 0
502 #define CONFIG_ENV_SIZE 0x20000
503 #elif defined(CONFIG_QSPI_BOOT)
504 #define CONFIG_ENV_IS_IN_SPI_FLASH
505 #define CONFIG_ENV_SIZE 0x2000
506 #define CONFIG_ENV_OFFSET 0x100000
507 #define CONFIG_ENV_SECT_SIZE 0x10000
509 #define CONFIG_ENV_IS_IN_FLASH
510 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
511 #define CONFIG_ENV_SIZE 0x20000
512 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
515 #define CONFIG_MISC_INIT_R
517 /* Hash command with SHA acceleration supported in hardware */
518 #ifdef CONFIG_FSL_CAAM
519 #define CONFIG_CMD_HASH
520 #define CONFIG_SHA_HW_ACCEL
523 #include <asm/fsl_secure_boot.h>
524 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */