1 /* SPDX-License-Identifier: GPL-2.0
2 * Copyright 2016-2019 NXP
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
9 #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10 #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12 /* XHCI Support - enabled by default */
14 #define DDR_SDRAM_CFG 0x470c0008
15 #define DDR_CS0_BNDS 0x008000bf
16 #define DDR_CS0_CONFIG 0x80014302
17 #define DDR_TIMING_CFG_0 0x50550004
18 #define DDR_TIMING_CFG_1 0xbcb38c56
19 #define DDR_TIMING_CFG_2 0x0040d120
20 #define DDR_TIMING_CFG_3 0x010e1000
21 #define DDR_TIMING_CFG_4 0x00000001
22 #define DDR_TIMING_CFG_5 0x03401400
23 #define DDR_SDRAM_CFG_2 0x00401010
24 #define DDR_SDRAM_MODE 0x00061c60
25 #define DDR_SDRAM_MODE_2 0x00180000
26 #define DDR_SDRAM_INTERVAL 0x18600618
27 #define DDR_DDR_WRLVL_CNTL 0x8655f605
28 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
29 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
30 #define DDR_DDR_CDR1 0x80040000
31 #define DDR_DDR_CDR2 0x00000001
32 #define DDR_SDRAM_CLK_CNTL 0x02000000
33 #define DDR_DDR_ZQ_CNTL 0x89080600
34 #define DDR_CS0_CONFIG_2 0
35 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
36 #define SDRAM_CFG2_D_INIT 0x00000010
37 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
38 #define SDRAM_CFG2_FRC_SR 0x80000000
39 #define SDRAM_CFG_BI 0x00000001
41 #define PHYS_SDRAM 0x80000000
42 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
44 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
45 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
48 #define CFG_SYS_NS16550_CLK get_serial_clock()
53 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
55 #define HWCONFIG_BUFFER_SIZE 256
57 #define BOOT_TARGET_DEVICES(func) \
61 #include <config_distro_bootcmd.h>
63 #define CFG_EXTRA_ENV_SETTINGS \
64 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
65 "initrd_high=0xffffffff\0" \
66 "kernel_addr=0x61000000\0" \
67 "kernelheader_addr=0x60800000\0" \
68 "scriptaddr=0x80000000\0" \
69 "scripthdraddr=0x80080000\0" \
70 "fdtheader_addr_r=0x80100000\0" \
71 "kernelheader_addr_r=0x80200000\0" \
72 "kernel_addr_r=0x80008000\0" \
73 "kernelheader_size=0x40000\0" \
74 "fdt_addr_r=0x8f000000\0" \
75 "ramdisk_addr_r=0xa0000000\0" \
76 "load_addr=0x80008000\0" \
77 "kernel_size=0x2800000\0" \
78 "kernel_addr_sd=0x8000\0" \
79 "kernel_size_sd=0x14000\0" \
80 "kernelhdr_addr_sd=0x4000\0" \
81 "kernelhdr_size_sd=0x10\0" \
83 "boot_scripts=ls1021atsn_boot.scr\0" \
84 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
85 "scan_dev_for_boot_part=" \
86 "part list ${devtype} ${devnum} devplist; " \
87 "env exists devplist || setenv devplist 1; " \
88 "for distro_bootpart in ${devplist}; do " \
89 "if fstype ${devtype} " \
90 "${devnum}:${distro_bootpart} " \
92 "run scan_dev_for_boot; " \
95 "scan_dev_for_boot=" \
96 "echo Scanning ${devtype} " \
97 "${devnum}:${distro_bootpart}...; " \
98 "for prefix in ${boot_prefixes}; do " \
99 "run scan_dev_for_scripts; " \
100 "run scan_dev_for_extlinux; " \
104 "load ${devtype} ${devnum}:${distro_bootpart} " \
105 "${scriptaddr} ${prefix}${script}; " \
106 "env exists secureboot && load ${devtype} " \
107 "${devnum}:${distro_bootpart} " \
108 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
109 "&& esbc_validate ${scripthdraddr};" \
110 "source ${scriptaddr}\0" \
111 "qspi_bootcmd=echo Trying load from qspi..;" \
112 "sf probe && sf read $load_addr " \
113 "$kernel_addr $kernel_size; env exists secureboot " \
114 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
115 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
116 "bootm $load_addr#$board\0" \
117 "sd_bootcmd=echo Trying load from SD ..;" \
118 "mmcinfo && mmc read $load_addr " \
119 "$kernel_addr_sd $kernel_size_sd && " \
120 "env exists secureboot && mmc read $kernelheader_addr_r " \
121 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
122 " && esbc_validate ${kernelheader_addr_r};" \
123 "bootm $load_addr#$board\0"
125 /* Miscellaneous configurable options */
126 #define CFG_SYS_BOOTMAPSZ (256 << 20)