include/configs/ls1021atsn.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  * Copyright 2016-2019 NXP Semiconductors
   3  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  10
  11 #define CONFIG_SYS_FSL_CLK
  12
  13 #define CONFIG_DEEP_SLEEP
  14
  15 /* Size of malloc() pool */
  16 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  17
  18 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  19 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  20
  21 /* XHCI Support - enabled by default */
  22 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  23
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #define CONFIG_DDR_CLK_FREQ             100000000
  26
  27 #define DDR_SDRAM_CFG                   0x470c0008
  28 #define DDR_CS0_BNDS                    0x008000bf
  29 #define DDR_CS0_CONFIG                  0x80014302
  30 #define DDR_TIMING_CFG_0                0x50550004
  31 #define DDR_TIMING_CFG_1                0xbcb38c56
  32 #define DDR_TIMING_CFG_2                0x0040d120
  33 #define DDR_TIMING_CFG_3                0x010e1000
  34 #define DDR_TIMING_CFG_4                0x00000001
  35 #define DDR_TIMING_CFG_5                0x03401400
  36 #define DDR_SDRAM_CFG_2                 0x00401010
  37 #define DDR_SDRAM_MODE                  0x00061c60
  38 #define DDR_SDRAM_MODE_2                0x00180000
  39 #define DDR_SDRAM_INTERVAL              0x18600618
  40 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  41 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  42 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  43 #define DDR_DDR_CDR1                    0x80040000
  44 #define DDR_DDR_CDR2                    0x00000001
  45 #define DDR_SDRAM_CLK_CNTL              0x02000000
  46 #define DDR_DDR_ZQ_CNTL                 0x89080600
  47 #define DDR_CS0_CONFIG_2                0
  48 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  49 #define SDRAM_CFG2_D_INIT               0x00000010
  50 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  51 #define SDRAM_CFG2_FRC_SR               0x80000000
  52 #define SDRAM_CFG_BI                    0x00000001
  53
  54 #ifdef CONFIG_RAMBOOT_PBL
  55 #define CONFIG_SYS_FSL_PBL_PBI  \
  56                 "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
  57 #endif
  58
  59 #ifdef CONFIG_SD_BOOT
  60 #define CONFIG_SYS_FSL_PBL_RCW  \
  61                 "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
  62
  63 #ifdef CONFIG_SECURE_BOOT
  64 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  65 #endif /* ifdef CONFIG_SECURE_BOOT */
  66
  67 #define CONFIG_SPL_MAX_SIZE             0x1a000
  68 #define CONFIG_SPL_STACK                0x1001d000
  69 #define CONFIG_SPL_PAD_TO               0x1c000
  70
  71 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  72                 CONFIG_SYS_MONITOR_LEN)
  73 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  74 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  75 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  76
  77 #ifdef CONFIG_U_BOOT_HDR_SIZE
  78 /*
  79  * HDR would be appended at end of image and copied to DDR along
  80  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  81  * size increases then increase this size in case of secure boot as
  82  * it uses raw U-Boot image instead of FIT image.
  83  */
  84 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  85 #else
  86 #define CONFIG_SYS_MONITOR_LEN          0x100000
  87 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  88 #endif
  89
  90 #define CONFIG_NR_DRAM_BANKS            1
  91 #define PHYS_SDRAM                      0x80000000
  92 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  93
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96
  97 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  98
  99 /* Serial Port */
 100 #define CONFIG_CONS_INDEX               1
 101 #define CONFIG_SYS_NS16550_SERIAL
 102 #ifndef CONFIG_DM_SERIAL
 103 #define CONFIG_SYS_NS16550_REG_SIZE     1
 104 #endif
 105 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 106
 107 /* I2C */
 108 #ifndef CONFIG_DM_I2C
 109 #define CONFIG_SYS_I2C
 110 #else
 111 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 112 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 113 #endif
 114 #define CONFIG_SYS_I2C_MXC
 115 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 116 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 117 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 118
 119 /* EEPROM */
 120 #define CONFIG_ID_EEPROM
 121 #define CONFIG_SYS_I2C_EEPROM_NXID
 122 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 123 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x51
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 125
 126 /* QSPI */
 127 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 128 #define FSL_QSPI_FLASH_NUM              2
 129
 130 /* PCIe */
 131 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 132 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 133 #define FSL_PCIE_COMPAT                 "fsl,ls1021a-pcie"
 134 #ifdef CONFIG_PCI
 135 #define CONFIG_PCI_SCAN_SHOW
 136 #endif
 137
 138 #define CONFIG_LAYERSCAPE_NS_ACCESS
 139 #define COUNTER_FREQUENCY               12500000
 140
 141 #define CONFIG_HWCONFIG
 142 #define HWCONFIG_BUFFER_SIZE            256
 143
 144 #define CONFIG_FSL_DEVICE_DISABLE
 145
 146 #define BOOT_TARGET_DEVICES(func) \
 147         func(MMC, mmc, 0) \
 148         func(USB, usb, 0) \
 149         func(DHCP, dhcp, na)
 150 #include <config_distro_bootcmd.h>
 151
 152 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 153         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0"             \
 154         "initrd_high=0xffffffff\0"                                      \
 155         "fdt_addr=0x64f00000\0"                                         \
 156         "kernel_addr=0x61000000\0"                                      \
 157         "kernelheader_addr=0x60800000\0"                                \
 158         "scriptaddr=0x80000000\0"                                       \
 159         "scripthdraddr=0x80080000\0"                                    \
 160         "fdtheader_addr_r=0x80100000\0"                                 \
 161         "kernelheader_addr_r=0x80200000\0"                              \
 162         "kernel_addr_r=0x80008000\0"                                    \
 163         "kernelheader_size=0x40000\0"                                   \
 164         "fdt_addr_r=0x8f000000\0"                                       \
 165         "ramdisk_addr_r=0xa0000000\0"                                   \
 166         "load_addr=0x80008000\0"                                        \
 167         "kernel_size=0x2800000\0"                                       \
 168         "kernel_addr_sd=0x8000\0"                                       \
 169         "kernel_size_sd=0x14000\0"                                      \
 170         "kernelhdr_addr_sd=0x4000\0"                                    \
 171         "kernelhdr_size_sd=0x10\0"                                      \
 172         BOOTENV                                                         \
 173         "boot_scripts=ls1021atsn_boot.scr\0"                            \
 174         "boot_script_hdr=hdr_ls1021atsn_bs.out\0"                       \
 175                 "scan_dev_for_boot_part="                               \
 176                         "part list ${devtype} ${devnum} devplist; "     \
 177                         "env exists devplist || setenv devplist 1; "    \
 178                         "for distro_bootpart in ${devplist}; do "       \
 179                         "if fstype ${devtype} "                         \
 180                                 "${devnum}:${distro_bootpart} "         \
 181                                 "bootfstype; then "                     \
 182                                 "run scan_dev_for_boot; "               \
 183                         "fi; "                                          \
 184                 "done\0"                                                \
 185         "scan_dev_for_boot="                                            \
 186                 "echo Scanning ${devtype} "                             \
 187                                 "${devnum}:${distro_bootpart}...; "     \
 188                 "for prefix in ${boot_prefixes}; do "                   \
 189                         "run scan_dev_for_scripts; "                    \
 190                         "run scan_dev_for_extlinux; "                   \
 191                 "done;"                                                 \
 192                 "\0"                                                    \
 193         "boot_a_script="                                                \
 194                 "load ${devtype} ${devnum}:${distro_bootpart} "         \
 195                         "${scriptaddr} ${prefix}${script}; "            \
 196                 "env exists secureboot && load ${devtype} "             \
 197                         "${devnum}:${distro_bootpart} "                 \
 198                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 199                         "&& esbc_validate ${scripthdraddr};"            \
 200                 "source ${scriptaddr}\0"                                \
 201         "qspi_bootcmd=echo Trying load from qspi..;"                    \
 202                 "sf probe && sf read $load_addr "                       \
 203                 "$kernel_addr $kernel_size; env exists secureboot "     \
 204                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 205                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 206                 "bootm $load_addr#$board\0"                             \
 207         "sd_bootcmd=echo Trying load from SD ..;"                       \
 208                 "mmcinfo && mmc read $load_addr "                       \
 209                 "$kernel_addr_sd $kernel_size_sd && "                   \
 210                 "env exists secureboot && mmc read $kernelheader_addr_r " \
 211                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 212                 " && esbc_validate ${kernelheader_addr_r};"             \
 213                 "bootm $load_addr#$board\0"
 214
 215 /* Miscellaneous configurable options */
 216 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 217
 218 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 219 #define CONFIG_SYS_PBSIZE               \
 220                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 221 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 222 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 223
 224 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 225
 226 #define CONFIG_LS102XA_STREAM_ID
 227
 228 #define CONFIG_SYS_INIT_SP_OFFSET \
 229         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230 #define CONFIG_SYS_INIT_SP_ADDR \
 231         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 232
 233 #ifdef CONFIG_SPL_BUILD
 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 235 #else
 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 237 #endif
 238
 239 /* Environment */
 240 #define CONFIG_ENV_OVERWRITE
 241
 242 #if defined(CONFIG_SD_BOOT)
 243 #define CONFIG_SYS_MMC_ENV_DEV          0
 244 #endif
 245
 246 #define CONFIG_SYS_BOOTM_LEN            0x8000000 /* 128 MB */
 247
 248 #endif