include/configs/ls1021atsn.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  * Copyright 2016-2019 NXP Semiconductors
   3  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  10
  11 #define CONFIG_SYS_FSL_CLK
  12
  13 #define CONFIG_DEEP_SLEEP
  14
  15 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  16 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  17
  18 /* XHCI Support - enabled by default */
  19 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  20
  21 #define CONFIG_SYS_CLK_FREQ             100000000
  22
  23 #define DDR_SDRAM_CFG                   0x470c0008
  24 #define DDR_CS0_BNDS                    0x008000bf
  25 #define DDR_CS0_CONFIG                  0x80014302
  26 #define DDR_TIMING_CFG_0                0x50550004
  27 #define DDR_TIMING_CFG_1                0xbcb38c56
  28 #define DDR_TIMING_CFG_2                0x0040d120
  29 #define DDR_TIMING_CFG_3                0x010e1000
  30 #define DDR_TIMING_CFG_4                0x00000001
  31 #define DDR_TIMING_CFG_5                0x03401400
  32 #define DDR_SDRAM_CFG_2                 0x00401010
  33 #define DDR_SDRAM_MODE                  0x00061c60
  34 #define DDR_SDRAM_MODE_2                0x00180000
  35 #define DDR_SDRAM_INTERVAL              0x18600618
  36 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  37 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  38 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  39 #define DDR_DDR_CDR1                    0x80040000
  40 #define DDR_DDR_CDR2                    0x00000001
  41 #define DDR_SDRAM_CLK_CNTL              0x02000000
  42 #define DDR_DDR_ZQ_CNTL                 0x89080600
  43 #define DDR_CS0_CONFIG_2                0
  44 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  45 #define SDRAM_CFG2_D_INIT               0x00000010
  46 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  47 #define SDRAM_CFG2_FRC_SR               0x80000000
  48 #define SDRAM_CFG_BI                    0x00000001
  49
  50 #ifdef CONFIG_SD_BOOT
  51 #ifdef CONFIG_NXP_ESBC
  52 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  53 #endif /* ifdef CONFIG_NXP_ESBC */
  54
  55 #define CONFIG_SPL_MAX_SIZE             0x1a000
  56 #define CONFIG_SPL_STACK                0x1001d000
  57 #define CONFIG_SPL_PAD_TO               0x1c000
  58
  59 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  60                 CONFIG_SYS_MONITOR_LEN)
  61 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  62 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  63 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  64
  65 #ifdef CONFIG_U_BOOT_HDR_SIZE
  66 /*
  67  * HDR would be appended at end of image and copied to DDR along
  68  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  69  * size increases then increase this size in case of secure boot as
  70  * it uses raw U-Boot image instead of FIT image.
  71  */
  72 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  73 #else
  74 #define CONFIG_SYS_MONITOR_LEN          0x100000
  75 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  76 #endif
  77
  78 #define CONFIG_NR_DRAM_BANKS            1
  79 #define PHYS_SDRAM                      0x80000000
  80 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  81
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  83 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  84
  85 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  86
  87 /* Serial Port */
  88 #define CONFIG_SYS_NS16550_SERIAL
  89 #ifndef CONFIG_DM_SERIAL
  90 #define CONFIG_SYS_NS16550_REG_SIZE     1
  91 #endif
  92 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  93
  94 /* I2C */
  95
  96 /* EEPROM */
  97 #define CONFIG_SYS_I2C_EEPROM_NXID
  98 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  99
 100 /* QSPI */
 101 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 102 #define FSL_QSPI_FLASH_NUM              2
 103
 104 /* PCIe */
 105 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 106 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 107 #define FSL_PCIE_COMPAT                 "fsl,ls1021a-pcie"
 108 #ifdef CONFIG_PCI
 109 #define CONFIG_PCI_SCAN_SHOW
 110 #endif
 111
 112 #define CONFIG_LAYERSCAPE_NS_ACCESS
 113 #define COUNTER_FREQUENCY               12500000
 114
 115 #define CONFIG_HWCONFIG
 116 #define HWCONFIG_BUFFER_SIZE            256
 117
 118 #define CONFIG_FSL_DEVICE_DISABLE
 119
 120 #define BOOT_TARGET_DEVICES(func) \
 121         func(MMC, mmc, 0) \
 122         func(USB, usb, 0) \
 123         func(DHCP, dhcp, na)
 124 #include <config_distro_bootcmd.h>
 125
 126 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 127         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0"             \
 128         "initrd_high=0xffffffff\0"                                      \
 129         "fdt_addr=0x64f00000\0"                                         \
 130         "kernel_addr=0x61000000\0"                                      \
 131         "kernelheader_addr=0x60800000\0"                                \
 132         "scriptaddr=0x80000000\0"                                       \
 133         "scripthdraddr=0x80080000\0"                                    \
 134         "fdtheader_addr_r=0x80100000\0"                                 \
 135         "kernelheader_addr_r=0x80200000\0"                              \
 136         "kernel_addr_r=0x80008000\0"                                    \
 137         "kernelheader_size=0x40000\0"                                   \
 138         "fdt_addr_r=0x8f000000\0"                                       \
 139         "ramdisk_addr_r=0xa0000000\0"                                   \
 140         "load_addr=0x80008000\0"                                        \
 141         "kernel_size=0x2800000\0"                                       \
 142         "kernel_addr_sd=0x8000\0"                                       \
 143         "kernel_size_sd=0x14000\0"                                      \
 144         "kernelhdr_addr_sd=0x4000\0"                                    \
 145         "kernelhdr_size_sd=0x10\0"                                      \
 146         BOOTENV                                                         \
 147         "boot_scripts=ls1021atsn_boot.scr\0"                            \
 148         "boot_script_hdr=hdr_ls1021atsn_bs.out\0"                       \
 149                 "scan_dev_for_boot_part="                               \
 150                         "part list ${devtype} ${devnum} devplist; "     \
 151                         "env exists devplist || setenv devplist 1; "    \
 152                         "for distro_bootpart in ${devplist}; do "       \
 153                         "if fstype ${devtype} "                         \
 154                                 "${devnum}:${distro_bootpart} "         \
 155                                 "bootfstype; then "                     \
 156                                 "run scan_dev_for_boot; "               \
 157                         "fi; "                                          \
 158                 "done\0"                                                \
 159         "scan_dev_for_boot="                                            \
 160                 "echo Scanning ${devtype} "                             \
 161                                 "${devnum}:${distro_bootpart}...; "     \
 162                 "for prefix in ${boot_prefixes}; do "                   \
 163                         "run scan_dev_for_scripts; "                    \
 164                         "run scan_dev_for_extlinux; "                   \
 165                 "done;"                                                 \
 166                 "\0"                                                    \
 167         "boot_a_script="                                                \
 168                 "load ${devtype} ${devnum}:${distro_bootpart} "         \
 169                         "${scriptaddr} ${prefix}${script}; "            \
 170                 "env exists secureboot && load ${devtype} "             \
 171                         "${devnum}:${distro_bootpart} "                 \
 172                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 173                         "&& esbc_validate ${scripthdraddr};"            \
 174                 "source ${scriptaddr}\0"                                \
 175         "qspi_bootcmd=echo Trying load from qspi..;"                    \
 176                 "sf probe && sf read $load_addr "                       \
 177                 "$kernel_addr $kernel_size; env exists secureboot "     \
 178                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 179                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 180                 "bootm $load_addr#$board\0"                             \
 181         "sd_bootcmd=echo Trying load from SD ..;"                       \
 182                 "mmcinfo && mmc read $load_addr "                       \
 183                 "$kernel_addr_sd $kernel_size_sd && "                   \
 184                 "env exists secureboot && mmc read $kernelheader_addr_r " \
 185                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 186                 " && esbc_validate ${kernelheader_addr_r};"             \
 187                 "bootm $load_addr#$board\0"
 188
 189 /* Miscellaneous configurable options */
 190 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 191
 192 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 193 #define CONFIG_SYS_PBSIZE               \
 194                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 195 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 196 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 197
 198 #define CONFIG_LS102XA_STREAM_ID
 199
 200 #define CONFIG_SYS_INIT_SP_OFFSET \
 201         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_INIT_SP_ADDR \
 203         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 204
 205 #ifdef CONFIG_SPL_BUILD
 206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 207 #else
 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 209 #endif
 210
 211 /* Environment */
 212
 213 #define CONFIG_SYS_BOOTM_LEN            0x8000000 /* 128 MB */
 214
 215 #endif