1 /* SPDX-License-Identifier: GPL-2.0
2 * Copyright 2016-2019 NXP
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
9 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12 /* XHCI Support - enabled by default */
13 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
15 #define DDR_SDRAM_CFG 0x470c0008
16 #define DDR_CS0_BNDS 0x008000bf
17 #define DDR_CS0_CONFIG 0x80014302
18 #define DDR_TIMING_CFG_0 0x50550004
19 #define DDR_TIMING_CFG_1 0xbcb38c56
20 #define DDR_TIMING_CFG_2 0x0040d120
21 #define DDR_TIMING_CFG_3 0x010e1000
22 #define DDR_TIMING_CFG_4 0x00000001
23 #define DDR_TIMING_CFG_5 0x03401400
24 #define DDR_SDRAM_CFG_2 0x00401010
25 #define DDR_SDRAM_MODE 0x00061c60
26 #define DDR_SDRAM_MODE_2 0x00180000
27 #define DDR_SDRAM_INTERVAL 0x18600618
28 #define DDR_DDR_WRLVL_CNTL 0x8655f605
29 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
30 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
31 #define DDR_DDR_CDR1 0x80040000
32 #define DDR_DDR_CDR2 0x00000001
33 #define DDR_SDRAM_CLK_CNTL 0x02000000
34 #define DDR_DDR_ZQ_CNTL 0x89080600
35 #define DDR_CS0_CONFIG_2 0
36 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
37 #define SDRAM_CFG2_D_INIT 0x00000010
38 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
39 #define SDRAM_CFG2_FRC_SR 0x80000000
40 #define SDRAM_CFG_BI 0x00000001
43 #ifdef CONFIG_NXP_ESBC
44 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
45 #endif /* ifdef CONFIG_NXP_ESBC */
47 #ifdef CONFIG_U_BOOT_HDR_SIZE
49 * HDR would be appended at end of image and copied to DDR along
50 * with U-Boot image. Here u-boot max. size is 512K. So if binary
51 * size increases then increase this size in case of secure boot as
52 * it uses raw U-Boot image instead of FIT image.
54 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
56 #define CONFIG_SYS_MONITOR_LEN 0x100000
57 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
60 #define PHYS_SDRAM 0x80000000
61 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
63 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
64 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67 #define CONFIG_SYS_NS16550_SERIAL
68 #ifndef CONFIG_DM_SERIAL
69 #define CONFIG_SYS_NS16550_REG_SIZE 1
71 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
76 #define CONFIG_SYS_I2C_EEPROM_NXID
77 #define CONFIG_SYS_EEPROM_BUS_NUM 0
80 #define FSL_QSPI_FLASH_SIZE (1 << 24)
81 #define FSL_QSPI_FLASH_NUM 2
84 #define CONFIG_PCIE1 /* PCIE controller 1 */
85 #define CONFIG_PCIE2 /* PCIE controller 2 */
86 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
88 #define CONFIG_PCI_SCAN_SHOW
91 #define CONFIG_LAYERSCAPE_NS_ACCESS
93 #define CONFIG_HWCONFIG
94 #define HWCONFIG_BUFFER_SIZE 256
96 #define CONFIG_FSL_DEVICE_DISABLE
98 #define BOOT_TARGET_DEVICES(func) \
102 #include <config_distro_bootcmd.h>
104 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
106 "initrd_high=0xffffffff\0" \
107 "kernel_addr=0x61000000\0" \
108 "kernelheader_addr=0x60800000\0" \
109 "scriptaddr=0x80000000\0" \
110 "scripthdraddr=0x80080000\0" \
111 "fdtheader_addr_r=0x80100000\0" \
112 "kernelheader_addr_r=0x80200000\0" \
113 "kernel_addr_r=0x80008000\0" \
114 "kernelheader_size=0x40000\0" \
115 "fdt_addr_r=0x8f000000\0" \
116 "ramdisk_addr_r=0xa0000000\0" \
117 "load_addr=0x80008000\0" \
118 "kernel_size=0x2800000\0" \
119 "kernel_addr_sd=0x8000\0" \
120 "kernel_size_sd=0x14000\0" \
121 "kernelhdr_addr_sd=0x4000\0" \
122 "kernelhdr_size_sd=0x10\0" \
124 "boot_scripts=ls1021atsn_boot.scr\0" \
125 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
126 "scan_dev_for_boot_part=" \
127 "part list ${devtype} ${devnum} devplist; " \
128 "env exists devplist || setenv devplist 1; " \
129 "for distro_bootpart in ${devplist}; do " \
130 "if fstype ${devtype} " \
131 "${devnum}:${distro_bootpart} " \
132 "bootfstype; then " \
133 "run scan_dev_for_boot; " \
136 "scan_dev_for_boot=" \
137 "echo Scanning ${devtype} " \
138 "${devnum}:${distro_bootpart}...; " \
139 "for prefix in ${boot_prefixes}; do " \
140 "run scan_dev_for_scripts; " \
141 "run scan_dev_for_extlinux; " \
145 "load ${devtype} ${devnum}:${distro_bootpart} " \
146 "${scriptaddr} ${prefix}${script}; " \
147 "env exists secureboot && load ${devtype} " \
148 "${devnum}:${distro_bootpart} " \
149 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
150 "&& esbc_validate ${scripthdraddr};" \
151 "source ${scriptaddr}\0" \
152 "qspi_bootcmd=echo Trying load from qspi..;" \
153 "sf probe && sf read $load_addr " \
154 "$kernel_addr $kernel_size; env exists secureboot " \
155 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
156 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
157 "bootm $load_addr#$board\0" \
158 "sd_bootcmd=echo Trying load from SD ..;" \
159 "mmcinfo && mmc read $load_addr " \
160 "$kernel_addr_sd $kernel_size_sd && " \
161 "env exists secureboot && mmc read $kernelheader_addr_r " \
162 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
163 " && esbc_validate ${kernelheader_addr_r};" \
164 "bootm $load_addr#$board\0"
166 /* Miscellaneous configurable options */
167 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
169 #define CONFIG_LS102XA_STREAM_ID
173 #define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */