1 /* SPDX-License-Identifier: GPL-2.0
2 * Copyright 2016-2019 NXP
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
9 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12 /* XHCI Support - enabled by default */
14 #define DDR_SDRAM_CFG 0x470c0008
15 #define DDR_CS0_BNDS 0x008000bf
16 #define DDR_CS0_CONFIG 0x80014302
17 #define DDR_TIMING_CFG_0 0x50550004
18 #define DDR_TIMING_CFG_1 0xbcb38c56
19 #define DDR_TIMING_CFG_2 0x0040d120
20 #define DDR_TIMING_CFG_3 0x010e1000
21 #define DDR_TIMING_CFG_4 0x00000001
22 #define DDR_TIMING_CFG_5 0x03401400
23 #define DDR_SDRAM_CFG_2 0x00401010
24 #define DDR_SDRAM_MODE 0x00061c60
25 #define DDR_SDRAM_MODE_2 0x00180000
26 #define DDR_SDRAM_INTERVAL 0x18600618
27 #define DDR_DDR_WRLVL_CNTL 0x8655f605
28 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
29 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
30 #define DDR_DDR_CDR1 0x80040000
31 #define DDR_DDR_CDR2 0x00000001
32 #define DDR_SDRAM_CLK_CNTL 0x02000000
33 #define DDR_DDR_ZQ_CNTL 0x89080600
34 #define DDR_CS0_CONFIG_2 0
35 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
36 #define SDRAM_CFG2_D_INIT 0x00000010
37 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
38 #define SDRAM_CFG2_FRC_SR 0x80000000
39 #define SDRAM_CFG_BI 0x00000001
42 #ifdef CONFIG_NXP_ESBC
43 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
44 #endif /* ifdef CONFIG_NXP_ESBC */
46 #ifdef CONFIG_U_BOOT_HDR_SIZE
48 * HDR would be appended at end of image and copied to DDR along
49 * with U-Boot image. Here u-boot max. size is 512K. So if binary
50 * size increases then increase this size in case of secure boot as
51 * it uses raw U-Boot image instead of FIT image.
53 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
55 #define CONFIG_SYS_MONITOR_LEN 0x100000
56 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
59 #define PHYS_SDRAM 0x80000000
60 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
62 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
63 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
66 #define CONFIG_SYS_NS16550_SERIAL
67 #ifndef CONFIG_DM_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE 1
70 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
75 #define CONFIG_SYS_I2C_EEPROM_NXID
76 #define CONFIG_SYS_EEPROM_BUS_NUM 0
79 #define FSL_QSPI_FLASH_SIZE (1 << 24)
80 #define FSL_QSPI_FLASH_NUM 2
83 #define CONFIG_PCIE1 /* PCIE controller 1 */
84 #define CONFIG_PCIE2 /* PCIE controller 2 */
85 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
87 #define CONFIG_PCI_SCAN_SHOW
90 #define CONFIG_HWCONFIG
91 #define HWCONFIG_BUFFER_SIZE 256
93 #define CONFIG_FSL_DEVICE_DISABLE
95 #define BOOT_TARGET_DEVICES(func) \
99 #include <config_distro_bootcmd.h>
101 #define CONFIG_EXTRA_ENV_SETTINGS \
102 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
103 "initrd_high=0xffffffff\0" \
104 "kernel_addr=0x61000000\0" \
105 "kernelheader_addr=0x60800000\0" \
106 "scriptaddr=0x80000000\0" \
107 "scripthdraddr=0x80080000\0" \
108 "fdtheader_addr_r=0x80100000\0" \
109 "kernelheader_addr_r=0x80200000\0" \
110 "kernel_addr_r=0x80008000\0" \
111 "kernelheader_size=0x40000\0" \
112 "fdt_addr_r=0x8f000000\0" \
113 "ramdisk_addr_r=0xa0000000\0" \
114 "load_addr=0x80008000\0" \
115 "kernel_size=0x2800000\0" \
116 "kernel_addr_sd=0x8000\0" \
117 "kernel_size_sd=0x14000\0" \
118 "kernelhdr_addr_sd=0x4000\0" \
119 "kernelhdr_size_sd=0x10\0" \
121 "boot_scripts=ls1021atsn_boot.scr\0" \
122 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
123 "scan_dev_for_boot_part=" \
124 "part list ${devtype} ${devnum} devplist; " \
125 "env exists devplist || setenv devplist 1; " \
126 "for distro_bootpart in ${devplist}; do " \
127 "if fstype ${devtype} " \
128 "${devnum}:${distro_bootpart} " \
129 "bootfstype; then " \
130 "run scan_dev_for_boot; " \
133 "scan_dev_for_boot=" \
134 "echo Scanning ${devtype} " \
135 "${devnum}:${distro_bootpart}...; " \
136 "for prefix in ${boot_prefixes}; do " \
137 "run scan_dev_for_scripts; " \
138 "run scan_dev_for_extlinux; " \
142 "load ${devtype} ${devnum}:${distro_bootpart} " \
143 "${scriptaddr} ${prefix}${script}; " \
144 "env exists secureboot && load ${devtype} " \
145 "${devnum}:${distro_bootpart} " \
146 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
147 "&& esbc_validate ${scripthdraddr};" \
148 "source ${scriptaddr}\0" \
149 "qspi_bootcmd=echo Trying load from qspi..;" \
150 "sf probe && sf read $load_addr " \
151 "$kernel_addr $kernel_size; env exists secureboot " \
152 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
153 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
154 "bootm $load_addr#$board\0" \
155 "sd_bootcmd=echo Trying load from SD ..;" \
156 "mmcinfo && mmc read $load_addr " \
157 "$kernel_addr_sd $kernel_size_sd && " \
158 "env exists secureboot && mmc read $kernelheader_addr_r " \
159 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
160 " && esbc_validate ${kernelheader_addr_r};" \
161 "bootm $load_addr#$board\0"
163 /* Miscellaneous configurable options */
164 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
166 #define CONFIG_LS102XA_STREAM_ID
170 #define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */