1 /* SPDX-License-Identifier: GPL-2.0
2 * Copyright 2016-2019 NXP Semiconductors
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
9 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11 #define CONFIG_SYS_FSL_CLK
13 #define CONFIG_DEEP_SLEEP
15 /* Size of malloc() pool */
16 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
18 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
19 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
21 /* XHCI Support - enabled by default */
22 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
24 #define CONFIG_SYS_CLK_FREQ 100000000
26 #define DDR_SDRAM_CFG 0x470c0008
27 #define DDR_CS0_BNDS 0x008000bf
28 #define DDR_CS0_CONFIG 0x80014302
29 #define DDR_TIMING_CFG_0 0x50550004
30 #define DDR_TIMING_CFG_1 0xbcb38c56
31 #define DDR_TIMING_CFG_2 0x0040d120
32 #define DDR_TIMING_CFG_3 0x010e1000
33 #define DDR_TIMING_CFG_4 0x00000001
34 #define DDR_TIMING_CFG_5 0x03401400
35 #define DDR_SDRAM_CFG_2 0x00401010
36 #define DDR_SDRAM_MODE 0x00061c60
37 #define DDR_SDRAM_MODE_2 0x00180000
38 #define DDR_SDRAM_INTERVAL 0x18600618
39 #define DDR_DDR_WRLVL_CNTL 0x8655f605
40 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
41 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
42 #define DDR_DDR_CDR1 0x80040000
43 #define DDR_DDR_CDR2 0x00000001
44 #define DDR_SDRAM_CLK_CNTL 0x02000000
45 #define DDR_DDR_ZQ_CNTL 0x89080600
46 #define DDR_CS0_CONFIG_2 0
47 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
48 #define SDRAM_CFG2_D_INIT 0x00000010
49 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
50 #define SDRAM_CFG2_FRC_SR 0x80000000
51 #define SDRAM_CFG_BI 0x00000001
53 #ifdef CONFIG_RAMBOOT_PBL
54 #define CONFIG_SYS_FSL_PBL_PBI \
55 "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
59 #define CONFIG_SYS_FSL_PBL_RCW \
60 "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
62 #ifdef CONFIG_NXP_ESBC
63 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
64 #endif /* ifdef CONFIG_NXP_ESBC */
66 #define CONFIG_SPL_MAX_SIZE 0x1a000
67 #define CONFIG_SPL_STACK 0x1001d000
68 #define CONFIG_SPL_PAD_TO 0x1c000
70 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
71 CONFIG_SYS_MONITOR_LEN)
72 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
73 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
74 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
76 #ifdef CONFIG_U_BOOT_HDR_SIZE
78 * HDR would be appended at end of image and copied to DDR along
79 * with U-Boot image. Here u-boot max. size is 512K. So if binary
80 * size increases then increase this size in case of secure boot as
81 * it uses raw U-Boot image instead of FIT image.
83 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85 #define CONFIG_SYS_MONITOR_LEN 0x100000
86 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
89 #define CONFIG_NR_DRAM_BANKS 1
90 #define PHYS_SDRAM 0x80000000
91 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
99 #define CONFIG_SYS_NS16550_SERIAL
100 #ifndef CONFIG_DM_SERIAL
101 #define CONFIG_SYS_NS16550_REG_SIZE 1
103 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
108 #define CONFIG_SYS_I2C_EEPROM_NXID
109 #define CONFIG_SYS_EEPROM_BUS_NUM 0
112 #define FSL_QSPI_FLASH_SIZE (1 << 24)
113 #define FSL_QSPI_FLASH_NUM 2
116 #define CONFIG_PCIE1 /* PCIE controller 1 */
117 #define CONFIG_PCIE2 /* PCIE controller 2 */
118 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
120 #define CONFIG_PCI_SCAN_SHOW
123 #define CONFIG_LAYERSCAPE_NS_ACCESS
124 #define COUNTER_FREQUENCY 12500000
126 #define CONFIG_HWCONFIG
127 #define HWCONFIG_BUFFER_SIZE 256
129 #define CONFIG_FSL_DEVICE_DISABLE
131 #define BOOT_TARGET_DEVICES(func) \
135 #include <config_distro_bootcmd.h>
137 #define CONFIG_EXTRA_ENV_SETTINGS \
138 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
139 "initrd_high=0xffffffff\0" \
140 "fdt_addr=0x64f00000\0" \
141 "kernel_addr=0x61000000\0" \
142 "kernelheader_addr=0x60800000\0" \
143 "scriptaddr=0x80000000\0" \
144 "scripthdraddr=0x80080000\0" \
145 "fdtheader_addr_r=0x80100000\0" \
146 "kernelheader_addr_r=0x80200000\0" \
147 "kernel_addr_r=0x80008000\0" \
148 "kernelheader_size=0x40000\0" \
149 "fdt_addr_r=0x8f000000\0" \
150 "ramdisk_addr_r=0xa0000000\0" \
151 "load_addr=0x80008000\0" \
152 "kernel_size=0x2800000\0" \
153 "kernel_addr_sd=0x8000\0" \
154 "kernel_size_sd=0x14000\0" \
155 "kernelhdr_addr_sd=0x4000\0" \
156 "kernelhdr_size_sd=0x10\0" \
158 "boot_scripts=ls1021atsn_boot.scr\0" \
159 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
160 "scan_dev_for_boot_part=" \
161 "part list ${devtype} ${devnum} devplist; " \
162 "env exists devplist || setenv devplist 1; " \
163 "for distro_bootpart in ${devplist}; do " \
164 "if fstype ${devtype} " \
165 "${devnum}:${distro_bootpart} " \
166 "bootfstype; then " \
167 "run scan_dev_for_boot; " \
170 "scan_dev_for_boot=" \
171 "echo Scanning ${devtype} " \
172 "${devnum}:${distro_bootpart}...; " \
173 "for prefix in ${boot_prefixes}; do " \
174 "run scan_dev_for_scripts; " \
175 "run scan_dev_for_extlinux; " \
179 "load ${devtype} ${devnum}:${distro_bootpart} " \
180 "${scriptaddr} ${prefix}${script}; " \
181 "env exists secureboot && load ${devtype} " \
182 "${devnum}:${distro_bootpart} " \
183 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
184 "&& esbc_validate ${scripthdraddr};" \
185 "source ${scriptaddr}\0" \
186 "qspi_bootcmd=echo Trying load from qspi..;" \
187 "sf probe && sf read $load_addr " \
188 "$kernel_addr $kernel_size; env exists secureboot " \
189 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
190 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
191 "bootm $load_addr#$board\0" \
192 "sd_bootcmd=echo Trying load from SD ..;" \
193 "mmcinfo && mmc read $load_addr " \
194 "$kernel_addr_sd $kernel_size_sd && " \
195 "env exists secureboot && mmc read $kernelheader_addr_r " \
196 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
197 " && esbc_validate ${kernelheader_addr_r};" \
198 "bootm $load_addr#$board\0"
200 /* Miscellaneous configurable options */
201 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
203 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
204 #define CONFIG_SYS_PBSIZE \
205 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
206 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
207 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
209 #define CONFIG_LS102XA_STREAM_ID
211 #define CONFIG_SYS_INIT_SP_OFFSET \
212 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
213 #define CONFIG_SYS_INIT_SP_ADDR \
214 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
216 #ifdef CONFIG_SPL_BUILD
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
224 #define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */