include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_SKIP_LOWLEVEL_INIT
  15
  16 #define CONFIG_DEEP_SLEEP
  17
  18 /*
  19  * Size of malloc() pool
  20  */
  21 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  22
  23 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  24 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  25
  26 #ifndef __ASSEMBLY__
  27 unsigned long get_board_sys_clk(void);
  28 #endif
  29
  30 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  31 #define CONFIG_SYS_CLK_FREQ             100000000
  32 #define CONFIG_QIXIS_I2C_ACCESS
  33 #else
  34 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  35 #endif
  36
  37 #ifdef CONFIG_RAMBOOT_PBL
  38 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  39 #endif
  40
  41 #ifdef CONFIG_SD_BOOT
  42 #ifdef CONFIG_SD_BOOT_QSPI
  43 #define CONFIG_SYS_FSL_PBL_RCW  \
  44         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  45 #else
  46 #define CONFIG_SYS_FSL_PBL_RCW  \
  47         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  48 #endif
  49
  50 #define CONFIG_SPL_MAX_SIZE             0x1a000
  51 #define CONFIG_SPL_STACK                0x1001d000
  52 #define CONFIG_SPL_PAD_TO               0x1c000
  53
  54 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  55                 CONFIG_SYS_MONITOR_LEN)
  56 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  57 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  58 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  59 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  60 #endif
  61
  62 #ifdef CONFIG_NAND_BOOT
  63 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  64
  65 #define CONFIG_SPL_MAX_SIZE             0x1a000
  66 #define CONFIG_SPL_STACK                0x1001d000
  67 #define CONFIG_SPL_PAD_TO               0x1c000
  68
  69 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  70 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  71 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  72 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  73 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  74
  75 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  76 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  77 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  78 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  79 #define CONFIG_SYS_MONITOR_LEN          0x80000
  80 #endif
  81
  82 #define CONFIG_DDR_SPD
  83 #define SPD_EEPROM_ADDRESS              0x51
  84 #define CONFIG_SYS_SPD_BUS_NUM          0
  85
  86 #ifndef CONFIG_SYS_FSL_DDR4
  87 #define CONFIG_SYS_DDR_RAW_TIMING
  88 #endif
  89 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  90 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  91
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  94
  95 #define CONFIG_DDR_ECC
  96 #ifdef CONFIG_DDR_ECC
  97 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  98 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  99 #endif
 100
 101 /*
 102  * IFC Definitions
 103  */
 104 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 105 #define CONFIG_FSL_IFC
 106 #define CONFIG_SYS_FLASH_BASE           0x60000000
 107 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 108
 109 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 110 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 111                                 CSPR_PORT_SIZE_16 | \
 112                                 CSPR_MSEL_NOR | \
 113                                 CSPR_V)
 114 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 115 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 116                                 + 0x8000000) | \
 117                                 CSPR_PORT_SIZE_16 | \
 118                                 CSPR_MSEL_NOR | \
 119                                 CSPR_V)
 120 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 121
 122 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 123                                         CSOR_NOR_TRHZ_80)
 124 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 125                                         FTIM0_NOR_TEADC(0x5) | \
 126                                         FTIM0_NOR_TEAHC(0x5))
 127 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 128                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 129                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 130 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 131                                         FTIM2_NOR_TCH(0x4) | \
 132                                         FTIM2_NOR_TWPH(0xe) | \
 133                                         FTIM2_NOR_TWP(0x1c))
 134 #define CONFIG_SYS_NOR_FTIM3            0
 135
 136 #define CONFIG_SYS_FLASH_QUIET_TEST
 137 #define CONFIG_FLASH_SHOW_PROGRESS      45
 138 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 139 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 140
 141 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 142 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 143 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 144 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 145
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO
 147 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 148                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 149
 150 /*
 151  * NAND Flash Definitions
 152  */
 153 #define CONFIG_NAND_FSL_IFC
 154
 155 #define CONFIG_SYS_NAND_BASE            0x7e800000
 156 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 157
 158 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 159
 160 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 161                                 | CSPR_PORT_SIZE_8      \
 162                                 | CSPR_MSEL_NAND        \
 163                                 | CSPR_V)
 164 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 165 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 166                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 167                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 168                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 169                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 170                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 171                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 172
 173 #define CONFIG_SYS_NAND_ONFI_DETECTION
 174
 175 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 176                                         FTIM0_NAND_TWP(0x18)   | \
 177                                         FTIM0_NAND_TWCHT(0x7) | \
 178                                         FTIM0_NAND_TWH(0xa))
 179 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 180                                         FTIM1_NAND_TWBE(0x39)  | \
 181                                         FTIM1_NAND_TRR(0xe)   | \
 182                                         FTIM1_NAND_TRP(0x18))
 183 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 184                                         FTIM2_NAND_TREH(0xa) | \
 185                                         FTIM2_NAND_TWHRE(0x1e))
 186 #define CONFIG_SYS_NAND_FTIM3           0x0
 187
 188 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 189 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 190
 191 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 192 #endif
 193
 194 /*
 195  * QIXIS Definitions
 196  */
 197 #define CONFIG_FSL_QIXIS
 198
 199 #ifdef CONFIG_FSL_QIXIS
 200 #define QIXIS_BASE                      0x7fb00000
 201 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 202 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 203 #define QIXIS_LBMAP_SWITCH              6
 204 #define QIXIS_LBMAP_MASK                0x0f
 205 #define QIXIS_LBMAP_SHIFT               0
 206 #define QIXIS_LBMAP_DFLTBANK            0x00
 207 #define QIXIS_LBMAP_ALTBANK             0x04
 208 #define QIXIS_PWR_CTL                   0x21
 209 #define QIXIS_PWR_CTL_POWEROFF          0x80
 210 #define QIXIS_RST_CTL_RESET             0x44
 211 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 212 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 213 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 214 #define QIXIS_CTL_SYS                   0x5
 215 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 216 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 217 #define QIXIS_RST_FORCE_3               0x45
 218 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 219 #define QIXIS_PWR_CTL2                  0x21
 220 #define QIXIS_PWR_CTL2_PCTL             0x2
 221
 222 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 223 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 224                                         CSPR_PORT_SIZE_8 | \
 225                                         CSPR_MSEL_GPCM | \
 226                                         CSPR_V)
 227 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 228 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 229                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 230                                         CSOR_NOR_TRHZ_80)
 231
 232 /*
 233  * QIXIS Timing parameters for IFC GPCM
 234  */
 235 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 236                                         FTIM0_GPCM_TEADC(0xe) | \
 237                                         FTIM0_GPCM_TEAHC(0xe))
 238 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 239                                         FTIM1_GPCM_TRAD(0x1f))
 240 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 241                                         FTIM2_GPCM_TCH(0xe) | \
 242                                         FTIM2_GPCM_TWP(0xf0))
 243 #define CONFIG_SYS_FPGA_FTIM3           0x0
 244 #endif
 245
 246 #if defined(CONFIG_NAND_BOOT)
 247 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 248 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 249 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 250 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 251 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 252 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 253 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 254 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 255 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 256 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 257 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 258 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 259 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 260 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 261 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 262 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 263 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 264 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 265 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 266 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 267 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 268 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 269 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 270 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 271 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 272 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 273 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 274 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 275 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 276 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 277 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 278 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 279 #else
 280 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 281 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 282 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 283 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 284 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 285 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 286 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 287 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 288 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 289 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 290 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 291 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 292 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 293 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 294 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 295 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 296 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 297 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 298 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 299 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 300 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 301 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 302 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 303 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 304 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 305 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 306 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 307 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 308 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 309 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 310 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 311 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 312 #endif
 313
 314 /*
 315  * Serial Port
 316  */
 317 #ifdef CONFIG_LPUART
 318 #define CONFIG_LPUART_32B_REG
 319 #else
 320 #define CONFIG_SYS_NS16550_SERIAL
 321 #ifndef CONFIG_DM_SERIAL
 322 #define CONFIG_SYS_NS16550_REG_SIZE     1
 323 #endif
 324 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 325 #endif
 326
 327 /*
 328  * I2C
 329  */
 330
 331 /* GPIO */
 332 #ifdef CONFIG_DM_GPIO
 333 #ifndef CONFIG_MPC8XXX_GPIO
 334 #define CONFIG_MPC8XXX_GPIO
 335 #endif
 336 #endif
 337
 338 /* EEPROM */
 339 #define CONFIG_SYS_I2C_EEPROM_NXID
 340 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 341
 342 /*
 343  * I2C bus multiplexer
 344  */
 345 #define I2C_MUX_PCA_ADDR_PRI            0x77
 346 #define I2C_MUX_CH_DEFAULT              0x8
 347 #define I2C_MUX_CH_CH7301               0xC
 348
 349 /*
 350  * MMC
 351  */
 352
 353 /*
 354  * Video
 355  */
 356 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 357 #define CONFIG_VIDEO_LOGO
 358 #define CONFIG_VIDEO_BMP_LOGO
 359
 360 #define CONFIG_FSL_DIU_CH7301
 361 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 362 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 363 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 364 #endif
 365
 366 /*
 367  * eTSEC
 368  */
 369
 370 #ifdef CONFIG_TSEC_ENET
 371 #define CONFIG_MII_DEFAULT_TSEC         3
 372 #define CONFIG_TSEC1                    1
 373 #define CONFIG_TSEC1_NAME               "eTSEC1"
 374 #define CONFIG_TSEC2                    1
 375 #define CONFIG_TSEC2_NAME               "eTSEC2"
 376 #define CONFIG_TSEC3                    1
 377 #define CONFIG_TSEC3_NAME               "eTSEC3"
 378
 379 #define TSEC1_PHY_ADDR                  1
 380 #define TSEC2_PHY_ADDR                  2
 381 #define TSEC3_PHY_ADDR                  3
 382
 383 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 384 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 385 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 386
 387 #define TSEC1_PHYIDX                    0
 388 #define TSEC2_PHYIDX                    0
 389 #define TSEC3_PHYIDX                    0
 390
 391 #define CONFIG_ETHPRIME                 "eTSEC1"
 392
 393 #define CONFIG_HAS_ETH0
 394 #define CONFIG_HAS_ETH1
 395 #define CONFIG_HAS_ETH2
 396
 397 #define CONFIG_FSL_SGMII_RISER          1
 398 #define SGMII_RISER_PHY_OFFSET          0x1b
 399
 400 #ifdef CONFIG_FSL_SGMII_RISER
 401 #define CONFIG_SYS_TBIPA_VALUE          8
 402 #endif
 403
 404 #endif
 405
 406 /* PCIe */
 407 #define CONFIG_PCIE1            /* PCIE controller 1 */
 408 #define CONFIG_PCIE2            /* PCIE controller 2 */
 409
 410 #ifdef CONFIG_PCI
 411 #define CONFIG_PCI_SCAN_SHOW
 412 #endif
 413
 414 #define CONFIG_CMDLINE_TAG
 415
 416 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 417 #define CONFIG_LAYERSCAPE_NS_ACCESS
 418 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 419 #define COUNTER_FREQUENCY               12500000
 420
 421 #define CONFIG_HWCONFIG
 422 #define HWCONFIG_BUFFER_SIZE            256
 423
 424 #define CONFIG_FSL_DEVICE_DISABLE
 425
 426
 427 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 428
 429 #ifdef CONFIG_LPUART
 430 #define CONFIG_EXTRA_ENV_SETTINGS       \
 431         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 432         "initrd_high=0xffffffff\0"      \
 433         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 434 #else
 435 #define CONFIG_EXTRA_ENV_SETTINGS       \
 436         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 437         "initrd_high=0xffffffff\0"      \
 438         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 439 #endif
 440
 441 /*
 442  * Miscellaneous configurable options
 443  */
 444 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 445
 446 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 447
 448 #define CONFIG_LS102XA_STREAM_ID
 449
 450 #define CONFIG_SYS_INIT_SP_OFFSET \
 451         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 452 #define CONFIG_SYS_INIT_SP_ADDR \
 453         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 454
 455 #ifdef CONFIG_SPL_BUILD
 456 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 457 #else
 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 459 #endif
 460
 461 /*
 462  * Environment
 463  */
 464
 465 #include <asm/fsl_secure_boot.h>
 466 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 467
 468 #endif