include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SPL_MAX_SIZE             0x1a000
  15 #define CONFIG_SPL_STACK                0x1001d000
  16 #define CONFIG_SPL_PAD_TO               0x1c000
  17
  18 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  19                 CONFIG_SYS_MONITOR_LEN)
  20 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  21 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  22 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  23 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  24 #endif
  25
  26 #ifdef CONFIG_NAND_BOOT
  27 #define CONFIG_SPL_MAX_SIZE             0x1a000
  28 #define CONFIG_SPL_STACK                0x1001d000
  29 #define CONFIG_SPL_PAD_TO               0x1c000
  30
  31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  32 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  34
  35 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  36 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  37 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  38 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  39 #define CONFIG_SYS_MONITOR_LEN          0x80000
  40 #endif
  41
  42 #define SPD_EEPROM_ADDRESS              0x51
  43 #define CONFIG_SYS_SPD_BUS_NUM          0
  44
  45 #ifndef CONFIG_SYS_FSL_DDR4
  46 #define CONFIG_SYS_DDR_RAW_TIMING
  47 #endif
  48
  49 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  51
  52 #ifdef CONFIG_DDR_ECC
  53 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  54 #endif
  55
  56 /*
  57  * IFC Definitions
  58  */
  59 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  60 #define CONFIG_SYS_FLASH_BASE           0x60000000
  61 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  62
  63 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  64 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  65                                 CSPR_PORT_SIZE_16 | \
  66                                 CSPR_MSEL_NOR | \
  67                                 CSPR_V)
  68 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  69 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  70                                 + 0x8000000) | \
  71                                 CSPR_PORT_SIZE_16 | \
  72                                 CSPR_MSEL_NOR | \
  73                                 CSPR_V)
  74 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  75
  76 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  77                                         CSOR_NOR_TRHZ_80)
  78 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  79                                         FTIM0_NOR_TEADC(0x5) | \
  80                                         FTIM0_NOR_TEAHC(0x5))
  81 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  82                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  83                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  84 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  85                                         FTIM2_NOR_TCH(0x4) | \
  86                                         FTIM2_NOR_TWPH(0xe) | \
  87                                         FTIM2_NOR_TWP(0x1c))
  88 #define CONFIG_SYS_NOR_FTIM3            0
  89
  90 #define CONFIG_SYS_FLASH_QUIET_TEST
  91 #define CONFIG_FLASH_SHOW_PROGRESS      45
  92 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  93
  94 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  95 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  97
  98 #define CONFIG_SYS_FLASH_EMPTY_INFO
  99 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 100                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 101
 102 /*
 103  * NAND Flash Definitions
 104  */
 105
 106 #define CONFIG_SYS_NAND_BASE            0x7e800000
 107 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 108
 109 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 110
 111 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 112                                 | CSPR_PORT_SIZE_8      \
 113                                 | CSPR_MSEL_NAND        \
 114                                 | CSPR_V)
 115 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 116 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 117                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 118                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 119                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 120                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 121                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 122                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 123
 124 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 125                                         FTIM0_NAND_TWP(0x18)   | \
 126                                         FTIM0_NAND_TWCHT(0x7) | \
 127                                         FTIM0_NAND_TWH(0xa))
 128 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 129                                         FTIM1_NAND_TWBE(0x39)  | \
 130                                         FTIM1_NAND_TRR(0xe)   | \
 131                                         FTIM1_NAND_TRP(0x18))
 132 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 133                                         FTIM2_NAND_TREH(0xa) | \
 134                                         FTIM2_NAND_TWHRE(0x1e))
 135 #define CONFIG_SYS_NAND_FTIM3           0x0
 136
 137 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 138 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 139 #endif
 140
 141 /*
 142  * QIXIS Definitions
 143  */
 144
 145 #ifdef CONFIG_FSL_QIXIS
 146 #define QIXIS_BASE                      0x7fb00000
 147 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 148 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 149 #define QIXIS_LBMAP_SWITCH              6
 150 #define QIXIS_LBMAP_MASK                0x0f
 151 #define QIXIS_LBMAP_SHIFT               0
 152 #define QIXIS_LBMAP_DFLTBANK            0x00
 153 #define QIXIS_LBMAP_ALTBANK             0x04
 154 #define QIXIS_PWR_CTL                   0x21
 155 #define QIXIS_PWR_CTL_POWEROFF          0x80
 156 #define QIXIS_RST_CTL_RESET             0x44
 157 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 158 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 159 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 160 #define QIXIS_CTL_SYS                   0x5
 161 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 162 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 163 #define QIXIS_RST_FORCE_3               0x45
 164 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 165 #define QIXIS_PWR_CTL2                  0x21
 166 #define QIXIS_PWR_CTL2_PCTL             0x2
 167
 168 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 169 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 170                                         CSPR_PORT_SIZE_8 | \
 171                                         CSPR_MSEL_GPCM | \
 172                                         CSPR_V)
 173 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 174 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 175                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 176                                         CSOR_NOR_TRHZ_80)
 177
 178 /*
 179  * QIXIS Timing parameters for IFC GPCM
 180  */
 181 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 182                                         FTIM0_GPCM_TEADC(0xe) | \
 183                                         FTIM0_GPCM_TEAHC(0xe))
 184 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 185                                         FTIM1_GPCM_TRAD(0x1f))
 186 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 187                                         FTIM2_GPCM_TCH(0xe) | \
 188                                         FTIM2_GPCM_TWP(0xf0))
 189 #define CONFIG_SYS_FPGA_FTIM3           0x0
 190 #endif
 191
 192 #if defined(CONFIG_NAND_BOOT)
 193 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 194 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 203 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 204 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 205 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 206 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 207 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 208 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 209 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 210 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 211 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 212 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 213 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 214 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 215 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 216 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 217 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 218 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 219 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 220 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 221 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 222 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 223 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 224 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 225 #else
 226 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 227 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 228 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 235 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 236 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 243 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 244 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 245 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 246 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 247 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 248 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 249 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 250 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 251 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 252 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 253 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 254 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 255 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 256 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 257 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 258 #endif
 259
 260 /*
 261  * Serial Port
 262  */
 263 #ifndef CONFIG_LPUART
 264 #define CONFIG_SYS_NS16550_SERIAL
 265 #ifndef CONFIG_DM_SERIAL
 266 #define CONFIG_SYS_NS16550_REG_SIZE     1
 267 #endif
 268 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 269 #endif
 270
 271 /*
 272  * I2C
 273  */
 274
 275 /* GPIO */
 276
 277 /* EEPROM */
 278 #define CONFIG_SYS_I2C_EEPROM_NXID
 279 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 280
 281 /*
 282  * I2C bus multiplexer
 283  */
 284 #define I2C_MUX_PCA_ADDR_PRI            0x77
 285 #define I2C_MUX_CH_DEFAULT              0x8
 286 #define I2C_MUX_CH_CH7301               0xC
 287
 288 /*
 289  * MMC
 290  */
 291
 292 /*
 293  * eTSEC
 294  */
 295
 296 #ifdef CONFIG_TSEC_ENET
 297 #define CONFIG_MII_DEFAULT_TSEC         3
 298 #define CONFIG_TSEC1                    1
 299 #define CONFIG_TSEC1_NAME               "eTSEC1"
 300 #define CONFIG_TSEC2                    1
 301 #define CONFIG_TSEC2_NAME               "eTSEC2"
 302 #define CONFIG_TSEC3                    1
 303 #define CONFIG_TSEC3_NAME               "eTSEC3"
 304
 305 #define TSEC1_PHY_ADDR                  1
 306 #define TSEC2_PHY_ADDR                  2
 307 #define TSEC3_PHY_ADDR                  3
 308
 309 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 310 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 311 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 312
 313 #define TSEC1_PHYIDX                    0
 314 #define TSEC2_PHYIDX                    0
 315 #define TSEC3_PHYIDX                    0
 316
 317 #define CONFIG_FSL_SGMII_RISER          1
 318 #define SGMII_RISER_PHY_OFFSET          0x1b
 319
 320 #ifdef CONFIG_FSL_SGMII_RISER
 321 #define CONFIG_SYS_TBIPA_VALUE          8
 322 #endif
 323
 324 #endif
 325
 326 /* PCIe */
 327 #define CONFIG_PCIE1            /* PCIE controller 1 */
 328 #define CONFIG_PCIE2            /* PCIE controller 2 */
 329
 330 #ifdef CONFIG_PCI
 331 #define CONFIG_PCI_SCAN_SHOW
 332 #endif
 333
 334 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 335 #define CONFIG_LAYERSCAPE_NS_ACCESS
 336 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 337
 338 #define CONFIG_HWCONFIG
 339 #define HWCONFIG_BUFFER_SIZE            256
 340
 341 #define CONFIG_FSL_DEVICE_DISABLE
 342
 343 #ifdef CONFIG_LPUART
 344 #define CONFIG_EXTRA_ENV_SETTINGS       \
 345         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 346         "initrd_high=0xffffffff\0"      \
 347         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 348 #else
 349 #define CONFIG_EXTRA_ENV_SETTINGS       \
 350         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 351         "initrd_high=0xffffffff\0"      \
 352         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 353 #endif
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 359
 360 #define CONFIG_LS102XA_STREAM_ID
 361
 362 #define CONFIG_SYS_INIT_SP_OFFSET \
 363         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 364 #define CONFIG_SYS_INIT_SP_ADDR \
 365         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 366
 367 /*
 368  * Environment
 369  */
 370
 371 #include <asm/fsl_secure_boot.h>
 372 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 373
 374 #endif