include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_SKIP_LOWLEVEL_INIT
  15
  16 #define CONFIG_DEEP_SLEEP
  17
  18 /*
  19  * Size of malloc() pool
  20  */
  21 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  22
  23 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  24 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  25
  26 #ifndef __ASSEMBLY__
  27 unsigned long get_board_sys_clk(void);
  28 #endif
  29
  30 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  31 #define CONFIG_SYS_CLK_FREQ             100000000
  32 #define CONFIG_QIXIS_I2C_ACCESS
  33 #else
  34 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  35 #endif
  36
  37 #ifdef CONFIG_SD_BOOT
  38 #define CONFIG_SPL_MAX_SIZE             0x1a000
  39 #define CONFIG_SPL_STACK                0x1001d000
  40 #define CONFIG_SPL_PAD_TO               0x1c000
  41
  42 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  43                 CONFIG_SYS_MONITOR_LEN)
  44 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  45 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  46 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  47 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  48 #endif
  49
  50 #ifdef CONFIG_NAND_BOOT
  51 #define CONFIG_SPL_MAX_SIZE             0x1a000
  52 #define CONFIG_SPL_STACK                0x1001d000
  53 #define CONFIG_SPL_PAD_TO               0x1c000
  54
  55 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  56 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  57 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  58 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  59 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  60
  61 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  62 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  63 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  64 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  65 #define CONFIG_SYS_MONITOR_LEN          0x80000
  66 #endif
  67
  68 #define SPD_EEPROM_ADDRESS              0x51
  69 #define CONFIG_SYS_SPD_BUS_NUM          0
  70
  71 #ifndef CONFIG_SYS_FSL_DDR4
  72 #define CONFIG_SYS_DDR_RAW_TIMING
  73 #endif
  74 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  75 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  76
  77 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  78 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  79
  80 #ifdef CONFIG_DDR_ECC
  81 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  82 #endif
  83
  84 /*
  85  * IFC Definitions
  86  */
  87 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  88 #define CONFIG_FSL_IFC
  89 #define CONFIG_SYS_FLASH_BASE           0x60000000
  90 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  91
  92 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  93 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  94                                 CSPR_PORT_SIZE_16 | \
  95                                 CSPR_MSEL_NOR | \
  96                                 CSPR_V)
  97 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  98 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  99                                 + 0x8000000) | \
 100                                 CSPR_PORT_SIZE_16 | \
 101                                 CSPR_MSEL_NOR | \
 102                                 CSPR_V)
 103 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 104
 105 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 106                                         CSOR_NOR_TRHZ_80)
 107 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 108                                         FTIM0_NOR_TEADC(0x5) | \
 109                                         FTIM0_NOR_TEAHC(0x5))
 110 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 111                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 112                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 113 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 114                                         FTIM2_NOR_TCH(0x4) | \
 115                                         FTIM2_NOR_TWPH(0xe) | \
 116                                         FTIM2_NOR_TWP(0x1c))
 117 #define CONFIG_SYS_NOR_FTIM3            0
 118
 119 #define CONFIG_SYS_FLASH_QUIET_TEST
 120 #define CONFIG_FLASH_SHOW_PROGRESS      45
 121 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 122 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 123
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 128
 129 #define CONFIG_SYS_FLASH_EMPTY_INFO
 130 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 131                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 132
 133 /*
 134  * NAND Flash Definitions
 135  */
 136 #define CONFIG_NAND_FSL_IFC
 137
 138 #define CONFIG_SYS_NAND_BASE            0x7e800000
 139 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 140
 141 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 142
 143 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 144                                 | CSPR_PORT_SIZE_8      \
 145                                 | CSPR_MSEL_NAND        \
 146                                 | CSPR_V)
 147 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 148 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 149                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 150                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 151                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 152                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 153                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 154                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 155
 156 #define CONFIG_SYS_NAND_ONFI_DETECTION
 157
 158 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 159                                         FTIM0_NAND_TWP(0x18)   | \
 160                                         FTIM0_NAND_TWCHT(0x7) | \
 161                                         FTIM0_NAND_TWH(0xa))
 162 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 163                                         FTIM1_NAND_TWBE(0x39)  | \
 164                                         FTIM1_NAND_TRR(0xe)   | \
 165                                         FTIM1_NAND_TRP(0x18))
 166 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 167                                         FTIM2_NAND_TREH(0xa) | \
 168                                         FTIM2_NAND_TWHRE(0x1e))
 169 #define CONFIG_SYS_NAND_FTIM3           0x0
 170
 171 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 172 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 173
 174 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 175 #endif
 176
 177 /*
 178  * QIXIS Definitions
 179  */
 180 #define CONFIG_FSL_QIXIS
 181
 182 #ifdef CONFIG_FSL_QIXIS
 183 #define QIXIS_BASE                      0x7fb00000
 184 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 185 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 186 #define QIXIS_LBMAP_SWITCH              6
 187 #define QIXIS_LBMAP_MASK                0x0f
 188 #define QIXIS_LBMAP_SHIFT               0
 189 #define QIXIS_LBMAP_DFLTBANK            0x00
 190 #define QIXIS_LBMAP_ALTBANK             0x04
 191 #define QIXIS_PWR_CTL                   0x21
 192 #define QIXIS_PWR_CTL_POWEROFF          0x80
 193 #define QIXIS_RST_CTL_RESET             0x44
 194 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 195 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 196 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 197 #define QIXIS_CTL_SYS                   0x5
 198 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 199 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 200 #define QIXIS_RST_FORCE_3               0x45
 201 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 202 #define QIXIS_PWR_CTL2                  0x21
 203 #define QIXIS_PWR_CTL2_PCTL             0x2
 204
 205 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 206 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 207                                         CSPR_PORT_SIZE_8 | \
 208                                         CSPR_MSEL_GPCM | \
 209                                         CSPR_V)
 210 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 211 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 212                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 213                                         CSOR_NOR_TRHZ_80)
 214
 215 /*
 216  * QIXIS Timing parameters for IFC GPCM
 217  */
 218 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 219                                         FTIM0_GPCM_TEADC(0xe) | \
 220                                         FTIM0_GPCM_TEAHC(0xe))
 221 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 222                                         FTIM1_GPCM_TRAD(0x1f))
 223 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 224                                         FTIM2_GPCM_TCH(0xe) | \
 225                                         FTIM2_GPCM_TWP(0xf0))
 226 #define CONFIG_SYS_FPGA_FTIM3           0x0
 227 #endif
 228
 229 #if defined(CONFIG_NAND_BOOT)
 230 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 231 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 232 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 233 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 234 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 235 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 236 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 237 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 238 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 239 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 240 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 241 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 242 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 243 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 244 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 245 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 246 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 247 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 248 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 249 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 250 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 251 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 252 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 253 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 254 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 255 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 256 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 257 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 258 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 259 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 260 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 261 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 262 #else
 263 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 264 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 265 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 266 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 267 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 268 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 269 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 270 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 271 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 272 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 273 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 280 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 281 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 282 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 283 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 284 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 285 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 286 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 287 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 288 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 289 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 290 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 291 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 292 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 293 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 294 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 295 #endif
 296
 297 /*
 298  * Serial Port
 299  */
 300 #ifdef CONFIG_LPUART
 301 #define CONFIG_LPUART_32B_REG
 302 #else
 303 #define CONFIG_SYS_NS16550_SERIAL
 304 #ifndef CONFIG_DM_SERIAL
 305 #define CONFIG_SYS_NS16550_REG_SIZE     1
 306 #endif
 307 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 308 #endif
 309
 310 /*
 311  * I2C
 312  */
 313
 314 /* GPIO */
 315 #ifdef CONFIG_DM_GPIO
 316 #ifndef CONFIG_MPC8XXX_GPIO
 317 #define CONFIG_MPC8XXX_GPIO
 318 #endif
 319 #endif
 320
 321 /* EEPROM */
 322 #define CONFIG_SYS_I2C_EEPROM_NXID
 323 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 324
 325 /*
 326  * I2C bus multiplexer
 327  */
 328 #define I2C_MUX_PCA_ADDR_PRI            0x77
 329 #define I2C_MUX_CH_DEFAULT              0x8
 330 #define I2C_MUX_CH_CH7301               0xC
 331
 332 /*
 333  * MMC
 334  */
 335
 336 /*
 337  * Video
 338  */
 339 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 340 #define CONFIG_VIDEO_LOGO
 341 #define CONFIG_VIDEO_BMP_LOGO
 342
 343 #define CONFIG_FSL_DIU_CH7301
 344 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 345 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 346 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 347 #endif
 348
 349 /*
 350  * eTSEC
 351  */
 352
 353 #ifdef CONFIG_TSEC_ENET
 354 #define CONFIG_MII_DEFAULT_TSEC         3
 355 #define CONFIG_TSEC1                    1
 356 #define CONFIG_TSEC1_NAME               "eTSEC1"
 357 #define CONFIG_TSEC2                    1
 358 #define CONFIG_TSEC2_NAME               "eTSEC2"
 359 #define CONFIG_TSEC3                    1
 360 #define CONFIG_TSEC3_NAME               "eTSEC3"
 361
 362 #define TSEC1_PHY_ADDR                  1
 363 #define TSEC2_PHY_ADDR                  2
 364 #define TSEC3_PHY_ADDR                  3
 365
 366 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 367 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 368 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 369
 370 #define TSEC1_PHYIDX                    0
 371 #define TSEC2_PHYIDX                    0
 372 #define TSEC3_PHYIDX                    0
 373
 374 #define CONFIG_ETHPRIME                 "eTSEC1"
 375
 376 #define CONFIG_HAS_ETH0
 377 #define CONFIG_HAS_ETH1
 378 #define CONFIG_HAS_ETH2
 379
 380 #define CONFIG_FSL_SGMII_RISER          1
 381 #define SGMII_RISER_PHY_OFFSET          0x1b
 382
 383 #ifdef CONFIG_FSL_SGMII_RISER
 384 #define CONFIG_SYS_TBIPA_VALUE          8
 385 #endif
 386
 387 #endif
 388
 389 /* PCIe */
 390 #define CONFIG_PCIE1            /* PCIE controller 1 */
 391 #define CONFIG_PCIE2            /* PCIE controller 2 */
 392
 393 #ifdef CONFIG_PCI
 394 #define CONFIG_PCI_SCAN_SHOW
 395 #endif
 396
 397 #define CONFIG_CMDLINE_TAG
 398
 399 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 400 #define CONFIG_LAYERSCAPE_NS_ACCESS
 401 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 402 #define COUNTER_FREQUENCY               12500000
 403
 404 #define CONFIG_HWCONFIG
 405 #define HWCONFIG_BUFFER_SIZE            256
 406
 407 #define CONFIG_FSL_DEVICE_DISABLE
 408
 409
 410 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 411
 412 #ifdef CONFIG_LPUART
 413 #define CONFIG_EXTRA_ENV_SETTINGS       \
 414         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 415         "initrd_high=0xffffffff\0"      \
 416         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 417 #else
 418 #define CONFIG_EXTRA_ENV_SETTINGS       \
 419         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 420         "initrd_high=0xffffffff\0"      \
 421         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 422 #endif
 423
 424 /*
 425  * Miscellaneous configurable options
 426  */
 427 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 428
 429 #define CONFIG_LS102XA_STREAM_ID
 430
 431 #define CONFIG_SYS_INIT_SP_OFFSET \
 432         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 433 #define CONFIG_SYS_INIT_SP_ADDR \
 434         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 435
 436 #ifdef CONFIG_SPL_BUILD
 437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 438 #else
 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 440 #endif
 441
 442 /*
 443  * Environment
 444  */
 445
 446 #include <asm/fsl_secure_boot.h>
 447 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 448
 449 #endif