include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_DEEP_SLEEP
  15
  16 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  17 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  18
  19 #ifndef __ASSEMBLY__
  20 unsigned long get_board_sys_clk(void);
  21 #endif
  22
  23 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #define CONFIG_QIXIS_I2C_ACCESS
  26 #else
  27 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  28 #endif
  29
  30 #ifdef CONFIG_SD_BOOT
  31 #define CONFIG_SPL_MAX_SIZE             0x1a000
  32 #define CONFIG_SPL_STACK                0x1001d000
  33 #define CONFIG_SPL_PAD_TO               0x1c000
  34
  35 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  36                 CONFIG_SYS_MONITOR_LEN)
  37 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  38 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  39 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  40 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  41 #endif
  42
  43 #ifdef CONFIG_NAND_BOOT
  44 #define CONFIG_SPL_MAX_SIZE             0x1a000
  45 #define CONFIG_SPL_STACK                0x1001d000
  46 #define CONFIG_SPL_PAD_TO               0x1c000
  47
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  50 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  51 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  52
  53 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  54 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  55 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  56 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  57 #define CONFIG_SYS_MONITOR_LEN          0x80000
  58 #endif
  59
  60 #define SPD_EEPROM_ADDRESS              0x51
  61 #define CONFIG_SYS_SPD_BUS_NUM          0
  62
  63 #ifndef CONFIG_SYS_FSL_DDR4
  64 #define CONFIG_SYS_DDR_RAW_TIMING
  65 #endif
  66 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  67 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  68
  69 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  70 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  71
  72 #ifdef CONFIG_DDR_ECC
  73 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  74 #endif
  75
  76 /*
  77  * IFC Definitions
  78  */
  79 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  80 #define CONFIG_FSL_IFC
  81 #define CONFIG_SYS_FLASH_BASE           0x60000000
  82 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  83
  84 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  85 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  86                                 CSPR_PORT_SIZE_16 | \
  87                                 CSPR_MSEL_NOR | \
  88                                 CSPR_V)
  89 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  90 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  91                                 + 0x8000000) | \
  92                                 CSPR_PORT_SIZE_16 | \
  93                                 CSPR_MSEL_NOR | \
  94                                 CSPR_V)
  95 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  96
  97 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  98                                         CSOR_NOR_TRHZ_80)
  99 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 100                                         FTIM0_NOR_TEADC(0x5) | \
 101                                         FTIM0_NOR_TEAHC(0x5))
 102 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 103                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 104                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 105 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 106                                         FTIM2_NOR_TCH(0x4) | \
 107                                         FTIM2_NOR_TWPH(0xe) | \
 108                                         FTIM2_NOR_TWP(0x1c))
 109 #define CONFIG_SYS_NOR_FTIM3            0
 110
 111 #define CONFIG_SYS_FLASH_QUIET_TEST
 112 #define CONFIG_FLASH_SHOW_PROGRESS      45
 113 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 114 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 115
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 120
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO
 122 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 123                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 124
 125 /*
 126  * NAND Flash Definitions
 127  */
 128 #define CONFIG_NAND_FSL_IFC
 129
 130 #define CONFIG_SYS_NAND_BASE            0x7e800000
 131 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 132
 133 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 134
 135 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 136                                 | CSPR_PORT_SIZE_8      \
 137                                 | CSPR_MSEL_NAND        \
 138                                 | CSPR_V)
 139 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 140 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 141                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 142                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 143                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 144                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 145                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 146                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 147
 148 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 149                                         FTIM0_NAND_TWP(0x18)   | \
 150                                         FTIM0_NAND_TWCHT(0x7) | \
 151                                         FTIM0_NAND_TWH(0xa))
 152 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 153                                         FTIM1_NAND_TWBE(0x39)  | \
 154                                         FTIM1_NAND_TRR(0xe)   | \
 155                                         FTIM1_NAND_TRP(0x18))
 156 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 157                                         FTIM2_NAND_TREH(0xa) | \
 158                                         FTIM2_NAND_TWHRE(0x1e))
 159 #define CONFIG_SYS_NAND_FTIM3           0x0
 160
 161 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 162 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 163 #endif
 164
 165 /*
 166  * QIXIS Definitions
 167  */
 168 #define CONFIG_FSL_QIXIS
 169
 170 #ifdef CONFIG_FSL_QIXIS
 171 #define QIXIS_BASE                      0x7fb00000
 172 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 173 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 174 #define QIXIS_LBMAP_SWITCH              6
 175 #define QIXIS_LBMAP_MASK                0x0f
 176 #define QIXIS_LBMAP_SHIFT               0
 177 #define QIXIS_LBMAP_DFLTBANK            0x00
 178 #define QIXIS_LBMAP_ALTBANK             0x04
 179 #define QIXIS_PWR_CTL                   0x21
 180 #define QIXIS_PWR_CTL_POWEROFF          0x80
 181 #define QIXIS_RST_CTL_RESET             0x44
 182 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 183 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 184 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 185 #define QIXIS_CTL_SYS                   0x5
 186 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 187 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 188 #define QIXIS_RST_FORCE_3               0x45
 189 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 190 #define QIXIS_PWR_CTL2                  0x21
 191 #define QIXIS_PWR_CTL2_PCTL             0x2
 192
 193 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 194 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 195                                         CSPR_PORT_SIZE_8 | \
 196                                         CSPR_MSEL_GPCM | \
 197                                         CSPR_V)
 198 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 199 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 200                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 201                                         CSOR_NOR_TRHZ_80)
 202
 203 /*
 204  * QIXIS Timing parameters for IFC GPCM
 205  */
 206 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 207                                         FTIM0_GPCM_TEADC(0xe) | \
 208                                         FTIM0_GPCM_TEAHC(0xe))
 209 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 210                                         FTIM1_GPCM_TRAD(0x1f))
 211 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 212                                         FTIM2_GPCM_TCH(0xe) | \
 213                                         FTIM2_GPCM_TWP(0xf0))
 214 #define CONFIG_SYS_FPGA_FTIM3           0x0
 215 #endif
 216
 217 #if defined(CONFIG_NAND_BOOT)
 218 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 219 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 220 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 221 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 222 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 223 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 224 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 225 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 226 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 227 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 228 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 235 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 236 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 243 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 244 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 245 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 246 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 247 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 248 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 249 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 250 #else
 251 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 252 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 253 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 254 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 255 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 256 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 257 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 258 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 259 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 260 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 261 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 262 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 263 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 264 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 265 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 266 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 267 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 268 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 269 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 270 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 271 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 272 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 273 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 274 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 275 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 276 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 277 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 278 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 279 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 280 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 281 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 282 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 283 #endif
 284
 285 /*
 286  * Serial Port
 287  */
 288 #ifdef CONFIG_LPUART
 289 #define CONFIG_LPUART_32B_REG
 290 #else
 291 #define CONFIG_SYS_NS16550_SERIAL
 292 #ifndef CONFIG_DM_SERIAL
 293 #define CONFIG_SYS_NS16550_REG_SIZE     1
 294 #endif
 295 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 296 #endif
 297
 298 /*
 299  * I2C
 300  */
 301
 302 /* GPIO */
 303 #ifdef CONFIG_DM_GPIO
 304 #ifndef CONFIG_MPC8XXX_GPIO
 305 #define CONFIG_MPC8XXX_GPIO
 306 #endif
 307 #endif
 308
 309 /* EEPROM */
 310 #define CONFIG_SYS_I2C_EEPROM_NXID
 311 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 312
 313 /*
 314  * I2C bus multiplexer
 315  */
 316 #define I2C_MUX_PCA_ADDR_PRI            0x77
 317 #define I2C_MUX_CH_DEFAULT              0x8
 318 #define I2C_MUX_CH_CH7301               0xC
 319
 320 /*
 321  * MMC
 322  */
 323
 324 /*
 325  * Video
 326  */
 327 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 328 #define CONFIG_VIDEO_LOGO
 329 #define CONFIG_VIDEO_BMP_LOGO
 330
 331 #define CONFIG_FSL_DIU_CH7301
 332 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 333 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 334 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 335 #endif
 336
 337 /*
 338  * eTSEC
 339  */
 340
 341 #ifdef CONFIG_TSEC_ENET
 342 #define CONFIG_MII_DEFAULT_TSEC         3
 343 #define CONFIG_TSEC1                    1
 344 #define CONFIG_TSEC1_NAME               "eTSEC1"
 345 #define CONFIG_TSEC2                    1
 346 #define CONFIG_TSEC2_NAME               "eTSEC2"
 347 #define CONFIG_TSEC3                    1
 348 #define CONFIG_TSEC3_NAME               "eTSEC3"
 349
 350 #define TSEC1_PHY_ADDR                  1
 351 #define TSEC2_PHY_ADDR                  2
 352 #define TSEC3_PHY_ADDR                  3
 353
 354 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 355 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 356 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 357
 358 #define TSEC1_PHYIDX                    0
 359 #define TSEC2_PHYIDX                    0
 360 #define TSEC3_PHYIDX                    0
 361
 362 #define CONFIG_ETHPRIME                 "eTSEC1"
 363
 364 #define CONFIG_HAS_ETH0
 365 #define CONFIG_HAS_ETH1
 366 #define CONFIG_HAS_ETH2
 367
 368 #define CONFIG_FSL_SGMII_RISER          1
 369 #define SGMII_RISER_PHY_OFFSET          0x1b
 370
 371 #ifdef CONFIG_FSL_SGMII_RISER
 372 #define CONFIG_SYS_TBIPA_VALUE          8
 373 #endif
 374
 375 #endif
 376
 377 /* PCIe */
 378 #define CONFIG_PCIE1            /* PCIE controller 1 */
 379 #define CONFIG_PCIE2            /* PCIE controller 2 */
 380
 381 #ifdef CONFIG_PCI
 382 #define CONFIG_PCI_SCAN_SHOW
 383 #endif
 384
 385 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 386 #define CONFIG_LAYERSCAPE_NS_ACCESS
 387 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 388 #define COUNTER_FREQUENCY               12500000
 389
 390 #define CONFIG_HWCONFIG
 391 #define HWCONFIG_BUFFER_SIZE            256
 392
 393 #define CONFIG_FSL_DEVICE_DISABLE
 394
 395
 396 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 397
 398 #ifdef CONFIG_LPUART
 399 #define CONFIG_EXTRA_ENV_SETTINGS       \
 400         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 401         "initrd_high=0xffffffff\0"      \
 402         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 403 #else
 404 #define CONFIG_EXTRA_ENV_SETTINGS       \
 405         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 406         "initrd_high=0xffffffff\0"      \
 407         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 408 #endif
 409
 410 /*
 411  * Miscellaneous configurable options
 412  */
 413 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 414
 415 #define CONFIG_LS102XA_STREAM_ID
 416
 417 #define CONFIG_SYS_INIT_SP_OFFSET \
 418         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 419 #define CONFIG_SYS_INIT_SP_ADDR \
 420         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 421
 422 #ifdef CONFIG_SPL_BUILD
 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 424 #else
 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 426 #endif
 427
 428 /*
 429  * Environment
 430  */
 431
 432 #include <asm/fsl_secure_boot.h>
 433 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 434
 435 #endif