include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_DEEP_SLEEP
  15
  16 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  17 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  18
  19 #ifndef __ASSEMBLY__
  20 unsigned long get_board_sys_clk(void);
  21 #endif
  22
  23 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #define CONFIG_QIXIS_I2C_ACCESS
  26 #else
  27 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  28 #endif
  29
  30 #ifdef CONFIG_SD_BOOT
  31 #define CONFIG_SPL_MAX_SIZE             0x1a000
  32 #define CONFIG_SPL_STACK                0x1001d000
  33 #define CONFIG_SPL_PAD_TO               0x1c000
  34
  35 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  36                 CONFIG_SYS_MONITOR_LEN)
  37 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  38 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  39 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  40 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  41 #endif
  42
  43 #ifdef CONFIG_NAND_BOOT
  44 #define CONFIG_SPL_MAX_SIZE             0x1a000
  45 #define CONFIG_SPL_STACK                0x1001d000
  46 #define CONFIG_SPL_PAD_TO               0x1c000
  47
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  50 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  51
  52 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  53 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  54 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  55 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  56 #define CONFIG_SYS_MONITOR_LEN          0x80000
  57 #endif
  58
  59 #define SPD_EEPROM_ADDRESS              0x51
  60 #define CONFIG_SYS_SPD_BUS_NUM          0
  61
  62 #ifndef CONFIG_SYS_FSL_DDR4
  63 #define CONFIG_SYS_DDR_RAW_TIMING
  64 #endif
  65 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  66 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  67
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  69 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  70
  71 #ifdef CONFIG_DDR_ECC
  72 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  73 #endif
  74
  75 /*
  76  * IFC Definitions
  77  */
  78 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  79 #define CONFIG_FSL_IFC
  80 #define CONFIG_SYS_FLASH_BASE           0x60000000
  81 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  82
  83 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  85                                 CSPR_PORT_SIZE_16 | \
  86                                 CSPR_MSEL_NOR | \
  87                                 CSPR_V)
  88 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  89 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  90                                 + 0x8000000) | \
  91                                 CSPR_PORT_SIZE_16 | \
  92                                 CSPR_MSEL_NOR | \
  93                                 CSPR_V)
  94 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  95
  96 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  97                                         CSOR_NOR_TRHZ_80)
  98 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  99                                         FTIM0_NOR_TEADC(0x5) | \
 100                                         FTIM0_NOR_TEAHC(0x5))
 101 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 102                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 103                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 104 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 105                                         FTIM2_NOR_TCH(0x4) | \
 106                                         FTIM2_NOR_TWPH(0xe) | \
 107                                         FTIM2_NOR_TWP(0x1c))
 108 #define CONFIG_SYS_NOR_FTIM3            0
 109
 110 #define CONFIG_SYS_FLASH_QUIET_TEST
 111 #define CONFIG_FLASH_SHOW_PROGRESS      45
 112 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 113 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 114
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 119
 120 #define CONFIG_SYS_FLASH_EMPTY_INFO
 121 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 122                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 123
 124 /*
 125  * NAND Flash Definitions
 126  */
 127
 128 #define CONFIG_SYS_NAND_BASE            0x7e800000
 129 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 130
 131 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 132
 133 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 134                                 | CSPR_PORT_SIZE_8      \
 135                                 | CSPR_MSEL_NAND        \
 136                                 | CSPR_V)
 137 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 138 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 139                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 140                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 141                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 142                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 143                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 144                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 145
 146 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 147                                         FTIM0_NAND_TWP(0x18)   | \
 148                                         FTIM0_NAND_TWCHT(0x7) | \
 149                                         FTIM0_NAND_TWH(0xa))
 150 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 151                                         FTIM1_NAND_TWBE(0x39)  | \
 152                                         FTIM1_NAND_TRR(0xe)   | \
 153                                         FTIM1_NAND_TRP(0x18))
 154 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 155                                         FTIM2_NAND_TREH(0xa) | \
 156                                         FTIM2_NAND_TWHRE(0x1e))
 157 #define CONFIG_SYS_NAND_FTIM3           0x0
 158
 159 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 160 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 161 #endif
 162
 163 /*
 164  * QIXIS Definitions
 165  */
 166 #define CONFIG_FSL_QIXIS
 167
 168 #ifdef CONFIG_FSL_QIXIS
 169 #define QIXIS_BASE                      0x7fb00000
 170 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 171 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 172 #define QIXIS_LBMAP_SWITCH              6
 173 #define QIXIS_LBMAP_MASK                0x0f
 174 #define QIXIS_LBMAP_SHIFT               0
 175 #define QIXIS_LBMAP_DFLTBANK            0x00
 176 #define QIXIS_LBMAP_ALTBANK             0x04
 177 #define QIXIS_PWR_CTL                   0x21
 178 #define QIXIS_PWR_CTL_POWEROFF          0x80
 179 #define QIXIS_RST_CTL_RESET             0x44
 180 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 181 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 182 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 183 #define QIXIS_CTL_SYS                   0x5
 184 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 185 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 186 #define QIXIS_RST_FORCE_3               0x45
 187 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 188 #define QIXIS_PWR_CTL2                  0x21
 189 #define QIXIS_PWR_CTL2_PCTL             0x2
 190
 191 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 192 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 193                                         CSPR_PORT_SIZE_8 | \
 194                                         CSPR_MSEL_GPCM | \
 195                                         CSPR_V)
 196 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 197 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 198                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 199                                         CSOR_NOR_TRHZ_80)
 200
 201 /*
 202  * QIXIS Timing parameters for IFC GPCM
 203  */
 204 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 205                                         FTIM0_GPCM_TEADC(0xe) | \
 206                                         FTIM0_GPCM_TEAHC(0xe))
 207 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 208                                         FTIM1_GPCM_TRAD(0x1f))
 209 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 210                                         FTIM2_GPCM_TCH(0xe) | \
 211                                         FTIM2_GPCM_TWP(0xf0))
 212 #define CONFIG_SYS_FPGA_FTIM3           0x0
 213 #endif
 214
 215 #if defined(CONFIG_NAND_BOOT)
 216 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 217 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 218 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 219 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 220 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 221 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 222 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 223 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 224 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 225 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 226 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 227 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 228 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 229 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 230 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 231 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 232 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 233 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 234 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 235 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 236 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 237 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 238 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 239 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 240 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 241 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 242 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 243 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 244 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 245 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 246 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 247 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 248 #else
 249 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 250 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 251 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 258 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 259 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 260 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 261 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 262 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 263 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 264 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 265 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 266 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 267 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 268 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 269 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 270 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 271 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 272 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 273 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 274 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 275 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 276 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 277 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 278 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 279 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 280 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 281 #endif
 282
 283 /*
 284  * Serial Port
 285  */
 286 #ifdef CONFIG_LPUART
 287 #define CONFIG_LPUART_32B_REG
 288 #else
 289 #define CONFIG_SYS_NS16550_SERIAL
 290 #ifndef CONFIG_DM_SERIAL
 291 #define CONFIG_SYS_NS16550_REG_SIZE     1
 292 #endif
 293 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 294 #endif
 295
 296 /*
 297  * I2C
 298  */
 299
 300 /* GPIO */
 301 #ifdef CONFIG_DM_GPIO
 302 #ifndef CONFIG_MPC8XXX_GPIO
 303 #define CONFIG_MPC8XXX_GPIO
 304 #endif
 305 #endif
 306
 307 /* EEPROM */
 308 #define CONFIG_SYS_I2C_EEPROM_NXID
 309 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 310
 311 /*
 312  * I2C bus multiplexer
 313  */
 314 #define I2C_MUX_PCA_ADDR_PRI            0x77
 315 #define I2C_MUX_CH_DEFAULT              0x8
 316 #define I2C_MUX_CH_CH7301               0xC
 317
 318 /*
 319  * MMC
 320  */
 321
 322 /*
 323  * Video
 324  */
 325 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 326 #define CONFIG_VIDEO_LOGO
 327 #define CONFIG_VIDEO_BMP_LOGO
 328
 329 #define CONFIG_FSL_DIU_CH7301
 330 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 331 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 332 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 333 #endif
 334
 335 /*
 336  * eTSEC
 337  */
 338
 339 #ifdef CONFIG_TSEC_ENET
 340 #define CONFIG_MII_DEFAULT_TSEC         3
 341 #define CONFIG_TSEC1                    1
 342 #define CONFIG_TSEC1_NAME               "eTSEC1"
 343 #define CONFIG_TSEC2                    1
 344 #define CONFIG_TSEC2_NAME               "eTSEC2"
 345 #define CONFIG_TSEC3                    1
 346 #define CONFIG_TSEC3_NAME               "eTSEC3"
 347
 348 #define TSEC1_PHY_ADDR                  1
 349 #define TSEC2_PHY_ADDR                  2
 350 #define TSEC3_PHY_ADDR                  3
 351
 352 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 353 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 354 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 355
 356 #define TSEC1_PHYIDX                    0
 357 #define TSEC2_PHYIDX                    0
 358 #define TSEC3_PHYIDX                    0
 359
 360 #define CONFIG_ETHPRIME                 "eTSEC1"
 361
 362 #define CONFIG_HAS_ETH0
 363 #define CONFIG_HAS_ETH1
 364 #define CONFIG_HAS_ETH2
 365
 366 #define CONFIG_FSL_SGMII_RISER          1
 367 #define SGMII_RISER_PHY_OFFSET          0x1b
 368
 369 #ifdef CONFIG_FSL_SGMII_RISER
 370 #define CONFIG_SYS_TBIPA_VALUE          8
 371 #endif
 372
 373 #endif
 374
 375 /* PCIe */
 376 #define CONFIG_PCIE1            /* PCIE controller 1 */
 377 #define CONFIG_PCIE2            /* PCIE controller 2 */
 378
 379 #ifdef CONFIG_PCI
 380 #define CONFIG_PCI_SCAN_SHOW
 381 #endif
 382
 383 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 384 #define CONFIG_LAYERSCAPE_NS_ACCESS
 385 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 386 #define COUNTER_FREQUENCY               12500000
 387
 388 #define CONFIG_HWCONFIG
 389 #define HWCONFIG_BUFFER_SIZE            256
 390
 391 #define CONFIG_FSL_DEVICE_DISABLE
 392
 393 #ifdef CONFIG_LPUART
 394 #define CONFIG_EXTRA_ENV_SETTINGS       \
 395         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 396         "initrd_high=0xffffffff\0"      \
 397         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 398 #else
 399 #define CONFIG_EXTRA_ENV_SETTINGS       \
 400         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 401         "initrd_high=0xffffffff\0"      \
 402         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 403 #endif
 404
 405 /*
 406  * Miscellaneous configurable options
 407  */
 408 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 409
 410 #define CONFIG_LS102XA_STREAM_ID
 411
 412 #define CONFIG_SYS_INIT_SP_OFFSET \
 413         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 414 #define CONFIG_SYS_INIT_SP_ADDR \
 415         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 416
 417 #ifdef CONFIG_SPL_BUILD
 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 419 #else
 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 421 #endif
 422
 423 /*
 424  * Environment
 425  */
 426
 427 #include <asm/fsl_secure_boot.h>
 428 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 429
 430 #endif