1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_SYS_FSL_CLK
14 #define CONFIG_SKIP_LOWLEVEL_INIT
16 #define CONFIG_DEEP_SLEEP
19 * Size of malloc() pool
21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
27 unsigned long get_board_sys_clk(void);
30 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
31 #define CONFIG_SYS_CLK_FREQ 100000000
32 #define CONFIG_QIXIS_I2C_ACCESS
34 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
37 #ifdef CONFIG_RAMBOOT_PBL
38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
42 #ifdef CONFIG_SD_BOOT_QSPI
43 #define CONFIG_SYS_FSL_PBL_RCW \
44 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
46 #define CONFIG_SYS_FSL_PBL_RCW \
47 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
50 #define CONFIG_SPL_MAX_SIZE 0x1a000
51 #define CONFIG_SPL_STACK 0x1001d000
52 #define CONFIG_SPL_PAD_TO 0x1c000
54 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
55 CONFIG_SYS_MONITOR_LEN)
56 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
57 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
58 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
59 #define CONFIG_SYS_MONITOR_LEN 0xc0000
62 #ifdef CONFIG_NAND_BOOT
63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
65 #define CONFIG_SPL_MAX_SIZE 0x1a000
66 #define CONFIG_SPL_STACK 0x1001d000
67 #define CONFIG_SPL_PAD_TO 0x1c000
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
70 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
71 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
72 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
73 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
75 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
76 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
77 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
78 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
79 #define CONFIG_SYS_MONITOR_LEN 0x80000
82 #define SPD_EEPROM_ADDRESS 0x51
83 #define CONFIG_SYS_SPD_BUS_NUM 0
85 #ifndef CONFIG_SYS_FSL_DDR4
86 #define CONFIG_SYS_DDR_RAW_TIMING
88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
89 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
101 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
102 #define CONFIG_FSL_IFC
103 #define CONFIG_SYS_FLASH_BASE 0x60000000
104 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
106 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
107 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
108 CSPR_PORT_SIZE_16 | \
111 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
112 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
114 CSPR_PORT_SIZE_16 | \
117 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
119 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
121 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
122 FTIM0_NOR_TEADC(0x5) | \
123 FTIM0_NOR_TEAHC(0x5))
124 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
125 FTIM1_NOR_TRAD_NOR(0x1a) | \
126 FTIM1_NOR_TSEQRAD_NOR(0x13))
127 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
128 FTIM2_NOR_TCH(0x4) | \
129 FTIM2_NOR_TWPH(0xe) | \
131 #define CONFIG_SYS_NOR_FTIM3 0
133 #define CONFIG_SYS_FLASH_QUIET_TEST
134 #define CONFIG_FLASH_SHOW_PROGRESS 45
135 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
136 #define CONFIG_SYS_WRITE_SWAPPED_DATA
138 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
139 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
140 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
141 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
143 #define CONFIG_SYS_FLASH_EMPTY_INFO
144 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
145 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
148 * NAND Flash Definitions
150 #define CONFIG_NAND_FSL_IFC
152 #define CONFIG_SYS_NAND_BASE 0x7e800000
153 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
155 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
157 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
161 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
162 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
163 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
164 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
165 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
166 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
167 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
168 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
170 #define CONFIG_SYS_NAND_ONFI_DETECTION
172 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
173 FTIM0_NAND_TWP(0x18) | \
174 FTIM0_NAND_TWCHT(0x7) | \
176 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
177 FTIM1_NAND_TWBE(0x39) | \
178 FTIM1_NAND_TRR(0xe) | \
179 FTIM1_NAND_TRP(0x18))
180 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
181 FTIM2_NAND_TREH(0xa) | \
182 FTIM2_NAND_TWHRE(0x1e))
183 #define CONFIG_SYS_NAND_FTIM3 0x0
185 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
186 #define CONFIG_SYS_MAX_NAND_DEVICE 1
188 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
194 #define CONFIG_FSL_QIXIS
196 #ifdef CONFIG_FSL_QIXIS
197 #define QIXIS_BASE 0x7fb00000
198 #define QIXIS_BASE_PHYS QIXIS_BASE
199 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
200 #define QIXIS_LBMAP_SWITCH 6
201 #define QIXIS_LBMAP_MASK 0x0f
202 #define QIXIS_LBMAP_SHIFT 0
203 #define QIXIS_LBMAP_DFLTBANK 0x00
204 #define QIXIS_LBMAP_ALTBANK 0x04
205 #define QIXIS_PWR_CTL 0x21
206 #define QIXIS_PWR_CTL_POWEROFF 0x80
207 #define QIXIS_RST_CTL_RESET 0x44
208 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
209 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
210 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
211 #define QIXIS_CTL_SYS 0x5
212 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
213 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
214 #define QIXIS_RST_FORCE_3 0x45
215 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
216 #define QIXIS_PWR_CTL2 0x21
217 #define QIXIS_PWR_CTL2_PCTL 0x2
219 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
220 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
224 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
225 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
226 CSOR_NOR_NOR_MODE_AVD_NOR | \
230 * QIXIS Timing parameters for IFC GPCM
232 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
233 FTIM0_GPCM_TEADC(0xe) | \
234 FTIM0_GPCM_TEAHC(0xe))
235 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
236 FTIM1_GPCM_TRAD(0x1f))
237 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
238 FTIM2_GPCM_TCH(0xe) | \
239 FTIM2_GPCM_TWP(0xf0))
240 #define CONFIG_SYS_FPGA_FTIM3 0x0
243 #if defined(CONFIG_NAND_BOOT)
244 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
245 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
249 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
250 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
251 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
252 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
253 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
254 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
261 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
262 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
263 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
264 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
265 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
266 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
267 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
268 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
269 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
270 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
271 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
272 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
273 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
274 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
275 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
277 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
278 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
279 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
280 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
281 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
282 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
283 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
284 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
285 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
286 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
287 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
288 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
289 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
290 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
291 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
292 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
293 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
294 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
295 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
296 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
297 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
298 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
299 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
300 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
301 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
302 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
303 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
304 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
305 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
306 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
307 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
308 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
315 #define CONFIG_LPUART_32B_REG
317 #define CONFIG_SYS_NS16550_SERIAL
318 #ifndef CONFIG_DM_SERIAL
319 #define CONFIG_SYS_NS16550_REG_SIZE 1
321 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
329 #ifdef CONFIG_DM_GPIO
330 #ifndef CONFIG_MPC8XXX_GPIO
331 #define CONFIG_MPC8XXX_GPIO
336 #define CONFIG_SYS_I2C_EEPROM_NXID
337 #define CONFIG_SYS_EEPROM_BUS_NUM 0
340 * I2C bus multiplexer
342 #define I2C_MUX_PCA_ADDR_PRI 0x77
343 #define I2C_MUX_CH_DEFAULT 0x8
344 #define I2C_MUX_CH_CH7301 0xC
353 #ifdef CONFIG_VIDEO_FSL_DCU_FB
354 #define CONFIG_VIDEO_LOGO
355 #define CONFIG_VIDEO_BMP_LOGO
357 #define CONFIG_FSL_DIU_CH7301
358 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
359 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
360 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
367 #ifdef CONFIG_TSEC_ENET
368 #define CONFIG_MII_DEFAULT_TSEC 3
369 #define CONFIG_TSEC1 1
370 #define CONFIG_TSEC1_NAME "eTSEC1"
371 #define CONFIG_TSEC2 1
372 #define CONFIG_TSEC2_NAME "eTSEC2"
373 #define CONFIG_TSEC3 1
374 #define CONFIG_TSEC3_NAME "eTSEC3"
376 #define TSEC1_PHY_ADDR 1
377 #define TSEC2_PHY_ADDR 2
378 #define TSEC3_PHY_ADDR 3
380 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
381 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
382 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
384 #define TSEC1_PHYIDX 0
385 #define TSEC2_PHYIDX 0
386 #define TSEC3_PHYIDX 0
388 #define CONFIG_ETHPRIME "eTSEC1"
390 #define CONFIG_HAS_ETH0
391 #define CONFIG_HAS_ETH1
392 #define CONFIG_HAS_ETH2
394 #define CONFIG_FSL_SGMII_RISER 1
395 #define SGMII_RISER_PHY_OFFSET 0x1b
397 #ifdef CONFIG_FSL_SGMII_RISER
398 #define CONFIG_SYS_TBIPA_VALUE 8
404 #define CONFIG_PCIE1 /* PCIE controller 1 */
405 #define CONFIG_PCIE2 /* PCIE controller 2 */
408 #define CONFIG_PCI_SCAN_SHOW
411 #define CONFIG_CMDLINE_TAG
413 #define CONFIG_PEN_ADDR_BIG_ENDIAN
414 #define CONFIG_LAYERSCAPE_NS_ACCESS
415 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
416 #define COUNTER_FREQUENCY 12500000
418 #define CONFIG_HWCONFIG
419 #define HWCONFIG_BUFFER_SIZE 256
421 #define CONFIG_FSL_DEVICE_DISABLE
424 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
427 #define CONFIG_EXTRA_ENV_SETTINGS \
428 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
429 "initrd_high=0xffffffff\0" \
430 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
432 #define CONFIG_EXTRA_ENV_SETTINGS \
433 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
434 "initrd_high=0xffffffff\0" \
435 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
439 * Miscellaneous configurable options
441 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
443 #define CONFIG_LS102XA_STREAM_ID
445 #define CONFIG_SYS_INIT_SP_OFFSET \
446 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
447 #define CONFIG_SYS_INIT_SP_ADDR \
448 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
450 #ifdef CONFIG_SPL_BUILD
451 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
453 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
460 #include <asm/fsl_secure_boot.h>
461 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */