2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_ARMV7_PSCI_1_0
12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
14 #define CONFIG_SYS_FSL_CLK
16 #define CONFIG_SKIP_LOWLEVEL_INIT
18 #define CONFIG_DEEP_SLEEP
21 * Size of malloc() pool
23 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
25 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
26 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
29 unsigned long get_board_sys_clk(void);
30 unsigned long get_board_ddr_clk(void);
33 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
34 #define CONFIG_SYS_CLK_FREQ 100000000
35 #define CONFIG_DDR_CLK_FREQ 100000000
36 #define CONFIG_QIXIS_I2C_ACCESS
38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
39 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
42 #ifdef CONFIG_RAMBOOT_PBL
43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
47 #ifdef CONFIG_SD_BOOT_QSPI
48 #define CONFIG_SYS_FSL_PBL_RCW \
49 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
51 #define CONFIG_SYS_FSL_PBL_RCW \
52 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
54 #define CONFIG_SPL_FRAMEWORK
56 #define CONFIG_SPL_TEXT_BASE 0x10000000
57 #define CONFIG_SPL_MAX_SIZE 0x1a000
58 #define CONFIG_SPL_STACK 0x1001d000
59 #define CONFIG_SPL_PAD_TO 0x1c000
60 #define CONFIG_SYS_TEXT_BASE 0x82000000
62 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
63 CONFIG_SYS_MONITOR_LEN)
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
66 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
67 #define CONFIG_SYS_MONITOR_LEN 0xc0000
70 #ifdef CONFIG_QSPI_BOOT
71 #define CONFIG_SYS_TEXT_BASE 0x40100000
74 #ifdef CONFIG_NAND_BOOT
75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
76 #define CONFIG_SPL_FRAMEWORK
78 #define CONFIG_SPL_TEXT_BASE 0x10000000
79 #define CONFIG_SPL_MAX_SIZE 0x1a000
80 #define CONFIG_SPL_STACK 0x1001d000
81 #define CONFIG_SPL_PAD_TO 0x1c000
82 #define CONFIG_SYS_TEXT_BASE 0x82000000
84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
85 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
86 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
87 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
88 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
90 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
94 #define CONFIG_SYS_MONITOR_LEN 0x80000
97 #ifndef CONFIG_SYS_TEXT_BASE
98 #define CONFIG_SYS_TEXT_BASE 0x60100000
101 #define CONFIG_NR_DRAM_BANKS 1
103 #define CONFIG_DDR_SPD
104 #define SPD_EEPROM_ADDRESS 0x51
105 #define CONFIG_SYS_SPD_BUS_NUM 0
107 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
108 #ifndef CONFIG_SYS_FSL_DDR4
109 #define CONFIG_SYS_DDR_RAW_TIMING
111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
112 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117 #define CONFIG_DDR_ECC
118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
123 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
124 !defined(CONFIG_QSPI_BOOT)
126 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
132 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
133 #define CONFIG_FSL_IFC
134 #define CONFIG_SYS_FLASH_BASE 0x60000000
135 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
137 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
138 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
139 CSPR_PORT_SIZE_16 | \
142 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
143 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
145 CSPR_PORT_SIZE_16 | \
148 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
150 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
152 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
153 FTIM0_NOR_TEADC(0x5) | \
154 FTIM0_NOR_TEAHC(0x5))
155 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
156 FTIM1_NOR_TRAD_NOR(0x1a) | \
157 FTIM1_NOR_TSEQRAD_NOR(0x13))
158 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
159 FTIM2_NOR_TCH(0x4) | \
160 FTIM2_NOR_TWPH(0xe) | \
162 #define CONFIG_SYS_NOR_FTIM3 0
164 #define CONFIG_FLASH_CFI_DRIVER
165 #define CONFIG_SYS_FLASH_CFI
166 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
167 #define CONFIG_SYS_FLASH_QUIET_TEST
168 #define CONFIG_FLASH_SHOW_PROGRESS 45
169 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
170 #define CONFIG_SYS_WRITE_SWAPPED_DATA
172 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
173 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 #define CONFIG_SYS_FLASH_EMPTY_INFO
178 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
179 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
182 * NAND Flash Definitions
184 #define CONFIG_NAND_FSL_IFC
186 #define CONFIG_SYS_NAND_BASE 0x7e800000
187 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
189 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
191 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
195 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
196 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
197 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
198 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
199 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
200 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
201 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
202 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
204 #define CONFIG_SYS_NAND_ONFI_DETECTION
206 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
207 FTIM0_NAND_TWP(0x18) | \
208 FTIM0_NAND_TWCHT(0x7) | \
210 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
211 FTIM1_NAND_TWBE(0x39) | \
212 FTIM1_NAND_TRR(0xe) | \
213 FTIM1_NAND_TRP(0x18))
214 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
215 FTIM2_NAND_TREH(0xa) | \
216 FTIM2_NAND_TWHRE(0x1e))
217 #define CONFIG_SYS_NAND_FTIM3 0x0
219 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
220 #define CONFIG_SYS_MAX_NAND_DEVICE 1
222 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
228 #define CONFIG_FSL_QIXIS
230 #ifdef CONFIG_FSL_QIXIS
231 #define QIXIS_BASE 0x7fb00000
232 #define QIXIS_BASE_PHYS QIXIS_BASE
233 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
234 #define QIXIS_LBMAP_SWITCH 6
235 #define QIXIS_LBMAP_MASK 0x0f
236 #define QIXIS_LBMAP_SHIFT 0
237 #define QIXIS_LBMAP_DFLTBANK 0x00
238 #define QIXIS_LBMAP_ALTBANK 0x04
239 #define QIXIS_PWR_CTL 0x21
240 #define QIXIS_PWR_CTL_POWEROFF 0x80
241 #define QIXIS_RST_CTL_RESET 0x44
242 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
243 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
244 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
245 #define QIXIS_CTL_SYS 0x5
246 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
247 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
248 #define QIXIS_RST_FORCE_3 0x45
249 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
250 #define QIXIS_PWR_CTL2 0x21
251 #define QIXIS_PWR_CTL2_PCTL 0x2
253 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
254 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
258 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
259 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
260 CSOR_NOR_NOR_MODE_AVD_NOR | \
264 * QIXIS Timing parameters for IFC GPCM
266 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
267 FTIM0_GPCM_TEADC(0xe) | \
268 FTIM0_GPCM_TEAHC(0xe))
269 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
270 FTIM1_GPCM_TRAD(0x1f))
271 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
272 FTIM2_GPCM_TCH(0xe) | \
273 FTIM2_GPCM_TWP(0xf0))
274 #define CONFIG_SYS_FPGA_FTIM3 0x0
277 #if defined(CONFIG_NAND_BOOT)
278 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
279 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
280 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
281 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
282 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
283 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
284 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
285 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
286 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
287 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
288 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
289 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
290 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
291 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
292 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
293 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
294 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
295 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
296 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
297 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
298 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
299 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
300 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
301 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
302 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
303 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
304 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
305 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
306 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
307 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
308 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
309 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
335 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
336 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
337 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
338 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
339 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
340 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
341 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
342 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
349 #define CONFIG_LPUART_32B_REG
351 #define CONFIG_CONS_INDEX 1
352 #define CONFIG_SYS_NS16550_SERIAL
353 #ifndef CONFIG_DM_SERIAL
354 #define CONFIG_SYS_NS16550_REG_SIZE 1
356 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
362 #define CONFIG_SYS_I2C
363 #define CONFIG_SYS_I2C_MXC
364 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
365 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
366 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
369 * I2C bus multiplexer
371 #define I2C_MUX_PCA_ADDR_PRI 0x77
372 #define I2C_MUX_CH_DEFAULT 0x8
373 #define I2C_MUX_CH_CH7301 0xC
378 #define CONFIG_FSL_ESDHC
381 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
383 #define QSPI0_AMBA_BASE 0x40000000
384 #define FSL_QSPI_FLASH_SIZE (1 << 24)
385 #define FSL_QSPI_FLASH_NUM 2
390 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
391 #define CONFIG_DM_SPI_FLASH
392 #define CONFIG_SPI_FLASH_DATAFLASH
399 /* EHCI Support - disbaled by default */
400 /*#define CONFIG_HAS_FSL_DR_USB*/
402 #ifdef CONFIG_HAS_FSL_DR_USB
403 #define CONFIG_USB_EHCI_FSL
404 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
407 /*XHCI Support - enabled by default*/
408 #define CONFIG_USB_XHCI_FSL
409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
414 #ifdef CONFIG_VIDEO_FSL_DCU_FB
415 #define CONFIG_VIDEO_LOGO
416 #define CONFIG_VIDEO_BMP_LOGO
418 #define CONFIG_FSL_DIU_CH7301
419 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
420 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
421 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
427 #define CONFIG_TSEC_ENET
429 #ifdef CONFIG_TSEC_ENET
431 #define CONFIG_MII_DEFAULT_TSEC 3
432 #define CONFIG_TSEC1 1
433 #define CONFIG_TSEC1_NAME "eTSEC1"
434 #define CONFIG_TSEC2 1
435 #define CONFIG_TSEC2_NAME "eTSEC2"
436 #define CONFIG_TSEC3 1
437 #define CONFIG_TSEC3_NAME "eTSEC3"
439 #define TSEC1_PHY_ADDR 1
440 #define TSEC2_PHY_ADDR 2
441 #define TSEC3_PHY_ADDR 3
443 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
444 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
445 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
447 #define TSEC1_PHYIDX 0
448 #define TSEC2_PHYIDX 0
449 #define TSEC3_PHYIDX 0
451 #define CONFIG_ETHPRIME "eTSEC1"
453 #define CONFIG_PHY_REALTEK
455 #define CONFIG_HAS_ETH0
456 #define CONFIG_HAS_ETH1
457 #define CONFIG_HAS_ETH2
459 #define CONFIG_FSL_SGMII_RISER 1
460 #define SGMII_RISER_PHY_OFFSET 0x1b
462 #ifdef CONFIG_FSL_SGMII_RISER
463 #define CONFIG_SYS_TBIPA_VALUE 8
469 #define CONFIG_PCIE1 /* PCIE controller 1 */
470 #define CONFIG_PCIE2 /* PCIE controller 2 */
473 #define CONFIG_PCI_SCAN_SHOW
476 #define CONFIG_CMDLINE_TAG
477 #define CONFIG_CMDLINE_EDITING
479 #define CONFIG_PEN_ADDR_BIG_ENDIAN
480 #define CONFIG_LAYERSCAPE_NS_ACCESS
481 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
482 #define COUNTER_FREQUENCY 12500000
484 #define CONFIG_HWCONFIG
485 #define HWCONFIG_BUFFER_SIZE 256
487 #define CONFIG_FSL_DEVICE_DISABLE
490 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
493 #define CONFIG_EXTRA_ENV_SETTINGS \
494 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
495 "fdt_high=0xffffffff\0" \
496 "initrd_high=0xffffffff\0" \
497 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
499 #define CONFIG_EXTRA_ENV_SETTINGS \
500 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
501 "fdt_high=0xffffffff\0" \
502 "initrd_high=0xffffffff\0" \
503 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
507 * Miscellaneous configurable options
509 #define CONFIG_SYS_LONGHELP /* undef to save memory */
510 #define CONFIG_AUTO_COMPLETE
512 #define CONFIG_SYS_MEMTEST_START 0x80000000
513 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
515 #define CONFIG_SYS_LOAD_ADDR 0x82000000
517 #define CONFIG_LS102XA_STREAM_ID
519 #define CONFIG_SYS_INIT_SP_OFFSET \
520 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
521 #define CONFIG_SYS_INIT_SP_ADDR \
522 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
524 #ifdef CONFIG_SPL_BUILD
525 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
527 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
533 #define CONFIG_ENV_OVERWRITE
535 #if defined(CONFIG_SD_BOOT)
536 #define CONFIG_ENV_OFFSET 0x300000
537 #define CONFIG_SYS_MMC_ENV_DEV 0
538 #define CONFIG_ENV_SIZE 0x2000
539 #elif defined(CONFIG_QSPI_BOOT)
540 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
541 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
542 #define CONFIG_ENV_SECT_SIZE 0x10000
543 #elif defined(CONFIG_NAND_BOOT)
544 #define CONFIG_ENV_SIZE 0x2000
545 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
547 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
548 #define CONFIG_ENV_SIZE 0x2000
549 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
552 #define CONFIG_MISC_INIT_R
554 #include <asm/fsl_secure_boot.h>
555 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */