include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19 #define CONFIG_BOARD_EARLY_INIT_F
  20
  21 #define CONFIG_DEEP_SLEEP
  22
  23 /*
  24  * Size of malloc() pool
  25  */
  26 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  27
  28 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  29 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  30
  31 /*
  32  * Generic Timer Definitions
  33  */
  34 #define GENERIC_TIMER_CLK               12500000
  35
  36 #ifndef __ASSEMBLY__
  37 unsigned long get_board_sys_clk(void);
  38 unsigned long get_board_ddr_clk(void);
  39 #endif
  40
  41 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  42 #define CONFIG_SYS_CLK_FREQ             100000000
  43 #define CONFIG_DDR_CLK_FREQ             100000000
  44 #define CONFIG_QIXIS_I2C_ACCESS
  45 #else
  46 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  47 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  48 #endif
  49
  50 #ifdef CONFIG_RAMBOOT_PBL
  51 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  52 #endif
  53
  54 #ifdef CONFIG_SD_BOOT
  55 #ifdef CONFIG_SD_BOOT_QSPI
  56 #define CONFIG_SYS_FSL_PBL_RCW  \
  57         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  58 #else
  59 #define CONFIG_SYS_FSL_PBL_RCW  \
  60         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  61 #endif
  62 #define CONFIG_SPL_FRAMEWORK
  63 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  64 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x600
  65
  66 #define CONFIG_SPL_TEXT_BASE            0x10000000
  67 #define CONFIG_SPL_MAX_SIZE             0x1a000
  68 #define CONFIG_SPL_STACK                0x1001d000
  69 #define CONFIG_SPL_PAD_TO               0x1c000
  70 #define CONFIG_SYS_TEXT_BASE            0x82000000
  71
  72 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  73                 CONFIG_SYS_MONITOR_LEN)
  74 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  75 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  76 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  77 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  78 #endif
  79
  80 #ifdef CONFIG_QSPI_BOOT
  81 #define CONFIG_SYS_TEXT_BASE            0x40010000
  82 #endif
  83
  84 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  85 #define CONFIG_SYS_NO_FLASH
  86 #endif
  87
  88 #ifdef CONFIG_NAND_BOOT
  89 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  90 #define CONFIG_SPL_FRAMEWORK
  91 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  92
  93 #define CONFIG_SPL_TEXT_BASE            0x10000000
  94 #define CONFIG_SPL_MAX_SIZE             0x1a000
  95 #define CONFIG_SPL_STACK                0x1001d000
  96 #define CONFIG_SPL_PAD_TO               0x1c000
  97 #define CONFIG_SYS_TEXT_BASE            0x82000000
  98
  99 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 101 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 102 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 103 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 104
 105 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 106 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 107 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 108 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 109 #define CONFIG_SYS_MONITOR_LEN          0x80000
 110 #endif
 111
 112 #ifndef CONFIG_SYS_TEXT_BASE
 113 #define CONFIG_SYS_TEXT_BASE            0x60100000
 114 #endif
 115
 116 #define CONFIG_NR_DRAM_BANKS            1
 117
 118 #define CONFIG_DDR_SPD
 119 #define SPD_EEPROM_ADDRESS              0x51
 120 #define CONFIG_SYS_SPD_BUS_NUM          0
 121
 122 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
 123 #ifndef CONFIG_SYS_FSL_DDR4
 124 #define CONFIG_SYS_DDR_RAW_TIMING
 125 #endif
 126 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 127 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 128
 129 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 130 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 131
 132 #define CONFIG_DDR_ECC
 133 #ifdef CONFIG_DDR_ECC
 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 135 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 136 #endif
 137
 138 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 139
 140 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 141         !defined(CONFIG_QSPI_BOOT)
 142 #define CONFIG_U_QE
 143 #endif
 144
 145 /*
 146  * IFC Definitions
 147  */
 148 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 149 #define CONFIG_FSL_IFC
 150 #define CONFIG_SYS_FLASH_BASE           0x60000000
 151 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 152
 153 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 154 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 155                                 CSPR_PORT_SIZE_16 | \
 156                                 CSPR_MSEL_NOR | \
 157                                 CSPR_V)
 158 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 159 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 160                                 + 0x8000000) | \
 161                                 CSPR_PORT_SIZE_16 | \
 162                                 CSPR_MSEL_NOR | \
 163                                 CSPR_V)
 164 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 165
 166 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 167                                         CSOR_NOR_TRHZ_80)
 168 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 169                                         FTIM0_NOR_TEADC(0x5) | \
 170                                         FTIM0_NOR_TEAHC(0x5))
 171 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 172                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 173                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 174 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 175                                         FTIM2_NOR_TCH(0x4) | \
 176                                         FTIM2_NOR_TWPH(0xe) | \
 177                                         FTIM2_NOR_TWP(0x1c))
 178 #define CONFIG_SYS_NOR_FTIM3            0
 179
 180 #define CONFIG_FLASH_CFI_DRIVER
 181 #define CONFIG_SYS_FLASH_CFI
 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 183 #define CONFIG_SYS_FLASH_QUIET_TEST
 184 #define CONFIG_FLASH_SHOW_PROGRESS      45
 185 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 186 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 187
 188 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 189 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 190 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 191 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 192
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO
 194 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 195                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 196
 197 /*
 198  * NAND Flash Definitions
 199  */
 200 #define CONFIG_NAND_FSL_IFC
 201
 202 #define CONFIG_SYS_NAND_BASE            0x7e800000
 203 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 204
 205 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 206
 207 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 208                                 | CSPR_PORT_SIZE_8      \
 209                                 | CSPR_MSEL_NAND        \
 210                                 | CSPR_V)
 211 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 212 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 213                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 214                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 215                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 216                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 217                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 218                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 219
 220 #define CONFIG_SYS_NAND_ONFI_DETECTION
 221
 222 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 223                                         FTIM0_NAND_TWP(0x18)   | \
 224                                         FTIM0_NAND_TWCHT(0x7) | \
 225                                         FTIM0_NAND_TWH(0xa))
 226 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 227                                         FTIM1_NAND_TWBE(0x39)  | \
 228                                         FTIM1_NAND_TRR(0xe)   | \
 229                                         FTIM1_NAND_TRP(0x18))
 230 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 231                                         FTIM2_NAND_TREH(0xa) | \
 232                                         FTIM2_NAND_TWHRE(0x1e))
 233 #define CONFIG_SYS_NAND_FTIM3           0x0
 234
 235 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 236 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 237 #define CONFIG_CMD_NAND
 238
 239 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 240 #endif
 241
 242 /*
 243  * QIXIS Definitions
 244  */
 245 #define CONFIG_FSL_QIXIS
 246
 247 #ifdef CONFIG_FSL_QIXIS
 248 #define QIXIS_BASE                      0x7fb00000
 249 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 250 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 251 #define QIXIS_LBMAP_SWITCH              6
 252 #define QIXIS_LBMAP_MASK                0x0f
 253 #define QIXIS_LBMAP_SHIFT               0
 254 #define QIXIS_LBMAP_DFLTBANK            0x00
 255 #define QIXIS_LBMAP_ALTBANK             0x04
 256 #define QIXIS_PWR_CTL                   0x21
 257 #define QIXIS_PWR_CTL_POWEROFF          0x80
 258 #define QIXIS_RST_CTL_RESET             0x44
 259 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 260 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 261 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 262 #define QIXIS_CTL_SYS                   0x5
 263 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 264 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 265 #define QIXIS_RST_FORCE_3               0x45
 266 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 267 #define QIXIS_PWR_CTL2                  0x21
 268 #define QIXIS_PWR_CTL2_PCTL             0x2
 269
 270 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 271 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 272                                         CSPR_PORT_SIZE_8 | \
 273                                         CSPR_MSEL_GPCM | \
 274                                         CSPR_V)
 275 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 276 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 277                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 278                                         CSOR_NOR_TRHZ_80)
 279
 280 /*
 281  * QIXIS Timing parameters for IFC GPCM
 282  */
 283 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 284                                         FTIM0_GPCM_TEADC(0xe) | \
 285                                         FTIM0_GPCM_TEAHC(0xe))
 286 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 287                                         FTIM1_GPCM_TRAD(0x1f))
 288 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 289                                         FTIM2_GPCM_TCH(0xe) | \
 290                                         FTIM2_GPCM_TWP(0xf0))
 291 #define CONFIG_SYS_FPGA_FTIM3           0x0
 292 #endif
 293
 294 #if defined(CONFIG_NAND_BOOT)
 295 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 296 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 297 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 298 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 299 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 300 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 301 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 302 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 303 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 304 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 305 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 306 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 307 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 308 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 309 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 310 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 311 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 312 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 313 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 314 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 315 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 316 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 317 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 318 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 319 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 320 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 321 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 322 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 323 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 324 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 325 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 326 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 327 #else
 328 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 329 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 330 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 331 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 332 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 333 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 334 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 335 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 336 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 337 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 338 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 339 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 340 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 341 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 342 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 343 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 344 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 345 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 346 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 347 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 348 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 349 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 350 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 351 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 352 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 353 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 354 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 355 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 356 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 357 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 358 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 359 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 360 #endif
 361
 362 /*
 363  * Serial Port
 364  */
 365 #ifdef CONFIG_LPUART
 366 #define CONFIG_LPUART_32B_REG
 367 #else
 368 #define CONFIG_CONS_INDEX               1
 369 #define CONFIG_SYS_NS16550_SERIAL
 370 #ifndef CONFIG_DM_SERIAL
 371 #define CONFIG_SYS_NS16550_REG_SIZE     1
 372 #endif
 373 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 374 #endif
 375
 376 #define CONFIG_BAUDRATE                 115200
 377
 378 /*
 379  * I2C
 380  */
 381 #define CONFIG_SYS_I2C
 382 #define CONFIG_SYS_I2C_MXC
 383 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 384 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 385 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 386
 387 /*
 388  * I2C bus multiplexer
 389  */
 390 #define I2C_MUX_PCA_ADDR_PRI            0x77
 391 #define I2C_MUX_CH_DEFAULT              0x8
 392 #define I2C_MUX_CH_CH7301               0xC
 393
 394 /*
 395  * MMC
 396  */
 397 #define CONFIG_MMC
 398 #define CONFIG_FSL_ESDHC
 399 #define CONFIG_GENERIC_MMC
 400
 401 #define CONFIG_DOS_PARTITION
 402
 403 /* SPI */
 404 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 405 /* QSPI */
 406 #define QSPI0_AMBA_BASE                 0x40000000
 407 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 408 #define FSL_QSPI_FLASH_NUM              2
 409
 410 /* DSPI */
 411
 412 /* DM SPI */
 413 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 414 #define CONFIG_DM_SPI_FLASH
 415 #define CONFIG_SPI_FLASH_DATAFLASH
 416 #endif
 417 #endif
 418
 419 /*
 420  * USB
 421  */
 422 /* EHCI Support - disbaled by default */
 423 /*#define CONFIG_HAS_FSL_DR_USB*/
 424
 425 #ifdef CONFIG_HAS_FSL_DR_USB
 426 #define CONFIG_USB_EHCI
 427 #define CONFIG_USB_EHCI_FSL
 428 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 429 #endif
 430
 431 /*XHCI Support - enabled by default*/
 432 #define CONFIG_HAS_FSL_XHCI_USB
 433
 434 #ifdef CONFIG_HAS_FSL_XHCI_USB
 435 #define CONFIG_USB_XHCI_FSL
 436 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 437 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 438 #endif
 439
 440 /*
 441  * Video
 442  */
 443 #define CONFIG_FSL_DCU_FB
 444
 445 #ifdef CONFIG_FSL_DCU_FB
 446 #define CONFIG_CMD_BMP
 447 #define CONFIG_VIDEO_LOGO
 448 #define CONFIG_VIDEO_BMP_LOGO
 449
 450 #define CONFIG_FSL_DIU_CH7301
 451 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 452 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 453 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 454 #endif
 455
 456 /*
 457  * eTSEC
 458  */
 459 #define CONFIG_TSEC_ENET
 460
 461 #ifdef CONFIG_TSEC_ENET
 462 #define CONFIG_MII
 463 #define CONFIG_MII_DEFAULT_TSEC         3
 464 #define CONFIG_TSEC1                    1
 465 #define CONFIG_TSEC1_NAME               "eTSEC1"
 466 #define CONFIG_TSEC2                    1
 467 #define CONFIG_TSEC2_NAME               "eTSEC2"
 468 #define CONFIG_TSEC3                    1
 469 #define CONFIG_TSEC3_NAME               "eTSEC3"
 470
 471 #define TSEC1_PHY_ADDR                  1
 472 #define TSEC2_PHY_ADDR                  2
 473 #define TSEC3_PHY_ADDR                  3
 474
 475 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 476 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 477 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 478
 479 #define TSEC1_PHYIDX                    0
 480 #define TSEC2_PHYIDX                    0
 481 #define TSEC3_PHYIDX                    0
 482
 483 #define CONFIG_ETHPRIME                 "eTSEC1"
 484
 485 #define CONFIG_PHY_GIGE
 486 #define CONFIG_PHYLIB
 487 #define CONFIG_PHY_REALTEK
 488
 489 #define CONFIG_HAS_ETH0
 490 #define CONFIG_HAS_ETH1
 491 #define CONFIG_HAS_ETH2
 492
 493 #define CONFIG_FSL_SGMII_RISER          1
 494 #define SGMII_RISER_PHY_OFFSET          0x1b
 495
 496 #ifdef CONFIG_FSL_SGMII_RISER
 497 #define CONFIG_SYS_TBIPA_VALUE          8
 498 #endif
 499
 500 #endif
 501
 502 /* PCIe */
 503 #define CONFIG_PCIE1            /* PCIE controller 1 */
 504 #define CONFIG_PCIE2            /* PCIE controller 2 */
 505 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 506 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 507
 508 #define CONFIG_SYS_PCI_64BIT
 509
 510 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 511 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 512 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 513 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 514
 515 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 516 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 517 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 518
 519 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 520 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 521 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 522
 523 #ifdef CONFIG_PCI
 524 #define CONFIG_PCI_SCAN_SHOW
 525 #define CONFIG_CMD_PCI
 526 #endif
 527
 528 #define CONFIG_CMDLINE_TAG
 529 #define CONFIG_CMDLINE_EDITING
 530
 531 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 532 #define CONFIG_LAYERSCAPE_NS_ACCESS
 533 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 534 #define CONFIG_TIMER_CLK_FREQ           12500000
 535
 536 #define CONFIG_HWCONFIG
 537 #define HWCONFIG_BUFFER_SIZE            256
 538
 539 #define CONFIG_FSL_DEVICE_DISABLE
 540
 541
 542 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 543
 544 #ifdef CONFIG_LPUART
 545 #define CONFIG_EXTRA_ENV_SETTINGS       \
 546         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 547         "fdt_high=0xffffffff\0"         \
 548         "initrd_high=0xffffffff\0"      \
 549         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 550 #else
 551 #define CONFIG_EXTRA_ENV_SETTINGS       \
 552         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 553         "fdt_high=0xffffffff\0"         \
 554         "initrd_high=0xffffffff\0"      \
 555         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 556 #endif
 557
 558 /*
 559  * Miscellaneous configurable options
 560  */
 561 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 562 #define CONFIG_AUTO_COMPLETE
 563 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 564 #define CONFIG_SYS_PBSIZE               \
 565                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 566 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 567 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 568
 569 #define CONFIG_SYS_MEMTEST_START        0x80000000
 570 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 571
 572 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 573
 574 #define CONFIG_LS102XA_STREAM_ID
 575
 576 /*
 577  * Stack sizes
 578  * The stack sizes are set up in start.S using the settings below
 579  */
 580 #define CONFIG_STACKSIZE                (30 * 1024)
 581
 582 #define CONFIG_SYS_INIT_SP_OFFSET \
 583         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 584 #define CONFIG_SYS_INIT_SP_ADDR \
 585         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 586
 587 #ifdef CONFIG_SPL_BUILD
 588 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 589 #else
 590 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 591 #endif
 592
 593 /*
 594  * Environment
 595  */
 596 #define CONFIG_ENV_OVERWRITE
 597
 598 #if defined(CONFIG_SD_BOOT)
 599 #define CONFIG_ENV_OFFSET               0x100000
 600 #define CONFIG_ENV_IS_IN_MMC
 601 #define CONFIG_SYS_MMC_ENV_DEV          0
 602 #define CONFIG_ENV_SIZE                 0x2000
 603 #elif defined(CONFIG_QSPI_BOOT)
 604 #define CONFIG_ENV_IS_IN_SPI_FLASH
 605 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 606 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 607 #define CONFIG_ENV_SECT_SIZE            0x10000
 608 #elif defined(CONFIG_NAND_BOOT)
 609 #define CONFIG_ENV_IS_IN_NAND
 610 #define CONFIG_ENV_SIZE                 0x2000
 611 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 612 #else
 613 #define CONFIG_ENV_IS_IN_FLASH
 614 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 615 #define CONFIG_ENV_SIZE                 0x2000
 616 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 617 #endif
 618
 619 #define CONFIG_MISC_INIT_R
 620
 621 /* Hash command with SHA acceleration supported in hardware */
 622 #ifdef CONFIG_FSL_CAAM
 623 #define CONFIG_CMD_HASH
 624 #define CONFIG_SHA_HW_ACCEL
 625 #endif
 626
 627 #include <asm/fsl_secure_boot.h>
 628 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 629
 630 #endif