include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16
  17 #ifdef CONFIG_SD_BOOT
  18 #define CONFIG_SPL_MAX_SIZE             0x1a000
  19 #define CONFIG_SPL_STACK                0x1001d000
  20 #define CONFIG_SPL_PAD_TO               0x1c000
  21
  22 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  23                 CONFIG_SYS_MONITOR_LEN)
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  25 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  26 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  27 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  28 #endif
  29
  30 #ifdef CONFIG_NAND_BOOT
  31 #define CONFIG_SPL_MAX_SIZE             0x1a000
  32 #define CONFIG_SPL_STACK                0x1001d000
  33 #define CONFIG_SPL_PAD_TO               0x1c000
  34
  35 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  36 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  37 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  38
  39 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  40 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  41 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  42 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  43 #define CONFIG_SYS_MONITOR_LEN          0x80000
  44 #endif
  45
  46 #define SPD_EEPROM_ADDRESS              0x51
  47 #define CONFIG_SYS_SPD_BUS_NUM          0
  48
  49 #ifndef CONFIG_SYS_FSL_DDR4
  50 #define CONFIG_SYS_DDR_RAW_TIMING
  51 #endif
  52
  53 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  54 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  55
  56 #ifdef CONFIG_DDR_ECC
  57 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  58 #endif
  59
  60 /*
  61  * IFC Definitions
  62  */
  63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  64 #define CONFIG_SYS_FLASH_BASE           0x60000000
  65 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  66
  67 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  68 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  69                                 CSPR_PORT_SIZE_16 | \
  70                                 CSPR_MSEL_NOR | \
  71                                 CSPR_V)
  72 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  73 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  74                                 + 0x8000000) | \
  75                                 CSPR_PORT_SIZE_16 | \
  76                                 CSPR_MSEL_NOR | \
  77                                 CSPR_V)
  78 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  79
  80 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  81                                         CSOR_NOR_TRHZ_80)
  82 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  83                                         FTIM0_NOR_TEADC(0x5) | \
  84                                         FTIM0_NOR_TEAHC(0x5))
  85 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  86                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  87                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  88 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  89                                         FTIM2_NOR_TCH(0x4) | \
  90                                         FTIM2_NOR_TWPH(0xe) | \
  91                                         FTIM2_NOR_TWP(0x1c))
  92 #define CONFIG_SYS_NOR_FTIM3            0
  93
  94 #define CONFIG_SYS_FLASH_QUIET_TEST
  95 #define CONFIG_FLASH_SHOW_PROGRESS      45
  96 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  97
  98 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  99 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 100 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 101
 102 #define CONFIG_SYS_FLASH_EMPTY_INFO
 103 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 104                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 105
 106 /*
 107  * NAND Flash Definitions
 108  */
 109
 110 #define CONFIG_SYS_NAND_BASE            0x7e800000
 111 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 112
 113 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 114
 115 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 116                                 | CSPR_PORT_SIZE_8      \
 117                                 | CSPR_MSEL_NAND        \
 118                                 | CSPR_V)
 119 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 120 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 121                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 122                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 123                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 124                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 125                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 126                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 127
 128 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 129                                         FTIM0_NAND_TWP(0x18)   | \
 130                                         FTIM0_NAND_TWCHT(0x7) | \
 131                                         FTIM0_NAND_TWH(0xa))
 132 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 133                                         FTIM1_NAND_TWBE(0x39)  | \
 134                                         FTIM1_NAND_TRR(0xe)   | \
 135                                         FTIM1_NAND_TRP(0x18))
 136 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 137                                         FTIM2_NAND_TREH(0xa) | \
 138                                         FTIM2_NAND_TWHRE(0x1e))
 139 #define CONFIG_SYS_NAND_FTIM3           0x0
 140
 141 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 143 #endif
 144
 145 /*
 146  * QIXIS Definitions
 147  */
 148 #define CONFIG_FSL_QIXIS
 149
 150 #ifdef CONFIG_FSL_QIXIS
 151 #define QIXIS_BASE                      0x7fb00000
 152 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 153 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 154 #define QIXIS_LBMAP_SWITCH              6
 155 #define QIXIS_LBMAP_MASK                0x0f
 156 #define QIXIS_LBMAP_SHIFT               0
 157 #define QIXIS_LBMAP_DFLTBANK            0x00
 158 #define QIXIS_LBMAP_ALTBANK             0x04
 159 #define QIXIS_PWR_CTL                   0x21
 160 #define QIXIS_PWR_CTL_POWEROFF          0x80
 161 #define QIXIS_RST_CTL_RESET             0x44
 162 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 163 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 164 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 165 #define QIXIS_CTL_SYS                   0x5
 166 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 167 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 168 #define QIXIS_RST_FORCE_3               0x45
 169 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 170 #define QIXIS_PWR_CTL2                  0x21
 171 #define QIXIS_PWR_CTL2_PCTL             0x2
 172
 173 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 174 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 175                                         CSPR_PORT_SIZE_8 | \
 176                                         CSPR_MSEL_GPCM | \
 177                                         CSPR_V)
 178 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 179 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 180                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 181                                         CSOR_NOR_TRHZ_80)
 182
 183 /*
 184  * QIXIS Timing parameters for IFC GPCM
 185  */
 186 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 187                                         FTIM0_GPCM_TEADC(0xe) | \
 188                                         FTIM0_GPCM_TEAHC(0xe))
 189 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 190                                         FTIM1_GPCM_TRAD(0x1f))
 191 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 192                                         FTIM2_GPCM_TCH(0xe) | \
 193                                         FTIM2_GPCM_TWP(0xf0))
 194 #define CONFIG_SYS_FPGA_FTIM3           0x0
 195 #endif
 196
 197 #if defined(CONFIG_NAND_BOOT)
 198 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 199 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 200 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 201 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 206 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 208 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 209 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 210 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 211 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 212 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 213 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 214 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 215 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 216 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 217 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 218 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 219 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 220 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 221 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 222 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 223 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 224 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 225 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 226 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 227 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 228 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 229 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 230 #else
 231 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 232 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 233 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 234 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 235 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 236 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 237 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 238 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 239 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 240 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 241 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 242 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 243 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 244 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 245 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 246 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 247 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 248 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 249 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 250 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 251 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 252 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 253 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 254 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 255 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 256 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 257 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 258 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 259 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 260 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 261 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 262 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 263 #endif
 264
 265 /*
 266  * Serial Port
 267  */
 268 #ifndef CONFIG_LPUART
 269 #define CONFIG_SYS_NS16550_SERIAL
 270 #ifndef CONFIG_DM_SERIAL
 271 #define CONFIG_SYS_NS16550_REG_SIZE     1
 272 #endif
 273 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 274 #endif
 275
 276 /*
 277  * I2C
 278  */
 279
 280 /* GPIO */
 281
 282 /* EEPROM */
 283 #define CONFIG_SYS_I2C_EEPROM_NXID
 284 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 285
 286 /*
 287  * I2C bus multiplexer
 288  */
 289 #define I2C_MUX_PCA_ADDR_PRI            0x77
 290 #define I2C_MUX_CH_DEFAULT              0x8
 291 #define I2C_MUX_CH_CH7301               0xC
 292
 293 /*
 294  * MMC
 295  */
 296
 297 /*
 298  * eTSEC
 299  */
 300
 301 #ifdef CONFIG_TSEC_ENET
 302 #define CONFIG_MII_DEFAULT_TSEC         3
 303 #define CONFIG_TSEC1                    1
 304 #define CONFIG_TSEC1_NAME               "eTSEC1"
 305 #define CONFIG_TSEC2                    1
 306 #define CONFIG_TSEC2_NAME               "eTSEC2"
 307 #define CONFIG_TSEC3                    1
 308 #define CONFIG_TSEC3_NAME               "eTSEC3"
 309
 310 #define TSEC1_PHY_ADDR                  1
 311 #define TSEC2_PHY_ADDR                  2
 312 #define TSEC3_PHY_ADDR                  3
 313
 314 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 315 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 316 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 317
 318 #define TSEC1_PHYIDX                    0
 319 #define TSEC2_PHYIDX                    0
 320 #define TSEC3_PHYIDX                    0
 321
 322 #define CONFIG_FSL_SGMII_RISER          1
 323 #define SGMII_RISER_PHY_OFFSET          0x1b
 324
 325 #ifdef CONFIG_FSL_SGMII_RISER
 326 #define CONFIG_SYS_TBIPA_VALUE          8
 327 #endif
 328
 329 #endif
 330
 331 /* PCIe */
 332 #define CONFIG_PCIE1            /* PCIE controller 1 */
 333 #define CONFIG_PCIE2            /* PCIE controller 2 */
 334
 335 #ifdef CONFIG_PCI
 336 #define CONFIG_PCI_SCAN_SHOW
 337 #endif
 338
 339 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 340 #define CONFIG_LAYERSCAPE_NS_ACCESS
 341 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 342 #define COUNTER_FREQUENCY               12500000
 343
 344 #define CONFIG_HWCONFIG
 345 #define HWCONFIG_BUFFER_SIZE            256
 346
 347 #define CONFIG_FSL_DEVICE_DISABLE
 348
 349 #ifdef CONFIG_LPUART
 350 #define CONFIG_EXTRA_ENV_SETTINGS       \
 351         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 352         "initrd_high=0xffffffff\0"      \
 353         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 354 #else
 355 #define CONFIG_EXTRA_ENV_SETTINGS       \
 356         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 357         "initrd_high=0xffffffff\0"      \
 358         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 359 #endif
 360
 361 /*
 362  * Miscellaneous configurable options
 363  */
 364 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 365
 366 #define CONFIG_LS102XA_STREAM_ID
 367
 368 #define CONFIG_SYS_INIT_SP_OFFSET \
 369         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 370 #define CONFIG_SYS_INIT_SP_ADDR \
 371         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 372
 373 /*
 374  * Environment
 375  */
 376
 377 #include <asm/fsl_secure_boot.h>
 378 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 379
 380 #endif