include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  15                 CONFIG_SYS_MONITOR_LEN)
  16 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  17 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  18 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  19 #endif
  20
  21 #ifdef CONFIG_NAND_BOOT
  22 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  23 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  25
  26 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  27 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  28 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  29 #define CONFIG_SYS_MONITOR_LEN          0x80000
  30 #endif
  31
  32 #define SPD_EEPROM_ADDRESS              0x51
  33 #define CONFIG_SYS_SPD_BUS_NUM          0
  34
  35 #ifndef CONFIG_SYS_FSL_DDR4
  36 #define CONFIG_SYS_DDR_RAW_TIMING
  37 #endif
  38
  39 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  40 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  41
  42 #ifdef CONFIG_DDR_ECC
  43 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  44 #endif
  45
  46 /*
  47  * IFC Definitions
  48  */
  49 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  50 #define CONFIG_SYS_FLASH_BASE           0x60000000
  51 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  52
  53 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  54 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  55                                 CSPR_PORT_SIZE_16 | \
  56                                 CSPR_MSEL_NOR | \
  57                                 CSPR_V)
  58 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  59 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  60                                 + 0x8000000) | \
  61                                 CSPR_PORT_SIZE_16 | \
  62                                 CSPR_MSEL_NOR | \
  63                                 CSPR_V)
  64 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  65
  66 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  67                                         CSOR_NOR_TRHZ_80)
  68 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  69                                         FTIM0_NOR_TEADC(0x5) | \
  70                                         FTIM0_NOR_TEAHC(0x5))
  71 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  72                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  73                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  74 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  75                                         FTIM2_NOR_TCH(0x4) | \
  76                                         FTIM2_NOR_TWPH(0xe) | \
  77                                         FTIM2_NOR_TWP(0x1c))
  78 #define CONFIG_SYS_NOR_FTIM3            0
  79
  80 #define CONFIG_SYS_FLASH_QUIET_TEST
  81 #define CONFIG_FLASH_SHOW_PROGRESS      45
  82 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  83
  84 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  85 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  86 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  87
  88 #define CONFIG_SYS_FLASH_EMPTY_INFO
  89 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  90                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  91
  92 /*
  93  * NAND Flash Definitions
  94  */
  95
  96 #define CONFIG_SYS_NAND_BASE            0x7e800000
  97 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  98
  99 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 100
 101 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 102                                 | CSPR_PORT_SIZE_8      \
 103                                 | CSPR_MSEL_NAND        \
 104                                 | CSPR_V)
 105 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 106 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 107                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 108                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 109                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 110                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 111                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 112                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 113
 114 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 115                                         FTIM0_NAND_TWP(0x18)   | \
 116                                         FTIM0_NAND_TWCHT(0x7) | \
 117                                         FTIM0_NAND_TWH(0xa))
 118 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 119                                         FTIM1_NAND_TWBE(0x39)  | \
 120                                         FTIM1_NAND_TRR(0xe)   | \
 121                                         FTIM1_NAND_TRP(0x18))
 122 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 123                                         FTIM2_NAND_TREH(0xa) | \
 124                                         FTIM2_NAND_TWHRE(0x1e))
 125 #define CONFIG_SYS_NAND_FTIM3           0x0
 126
 127 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 128 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 129 #endif
 130
 131 /*
 132  * QIXIS Definitions
 133  */
 134
 135 #ifdef CONFIG_FSL_QIXIS
 136 #define QIXIS_BASE                      0x7fb00000
 137 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 138 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 139 #define QIXIS_LBMAP_SWITCH              6
 140 #define QIXIS_LBMAP_MASK                0x0f
 141 #define QIXIS_LBMAP_SHIFT               0
 142 #define QIXIS_LBMAP_DFLTBANK            0x00
 143 #define QIXIS_LBMAP_ALTBANK             0x04
 144 #define QIXIS_PWR_CTL                   0x21
 145 #define QIXIS_PWR_CTL_POWEROFF          0x80
 146 #define QIXIS_RST_CTL_RESET             0x44
 147 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 148 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 149 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 150 #define QIXIS_CTL_SYS                   0x5
 151 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 152 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 153 #define QIXIS_RST_FORCE_3               0x45
 154 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 155 #define QIXIS_PWR_CTL2                  0x21
 156 #define QIXIS_PWR_CTL2_PCTL             0x2
 157
 158 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 159 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 160                                         CSPR_PORT_SIZE_8 | \
 161                                         CSPR_MSEL_GPCM | \
 162                                         CSPR_V)
 163 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 164 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 165                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 166                                         CSOR_NOR_TRHZ_80)
 167
 168 /*
 169  * QIXIS Timing parameters for IFC GPCM
 170  */
 171 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 172                                         FTIM0_GPCM_TEADC(0xe) | \
 173                                         FTIM0_GPCM_TEAHC(0xe))
 174 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 175                                         FTIM1_GPCM_TRAD(0x1f))
 176 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 177                                         FTIM2_GPCM_TCH(0xe) | \
 178                                         FTIM2_GPCM_TWP(0xf0))
 179 #define CONFIG_SYS_FPGA_FTIM3           0x0
 180 #endif
 181
 182 #if defined(CONFIG_NAND_BOOT)
 183 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 184 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 185 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 186 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 187 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 188 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 189 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 190 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 191 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 193 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 194 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 195 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 196 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 197 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 198 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 199 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 200 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 201 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 202 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 203 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 204 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 205 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 206 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 207 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 208 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 209 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 210 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 211 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 212 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 213 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 214 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 215 #else
 216 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 217 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 218 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 219 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 220 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 221 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 222 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 223 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 224 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 225 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 226 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 227 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 228 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 229 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 230 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 231 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 232 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 233 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 234 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 235 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 236 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 237 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 238 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 239 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 240 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 241 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 242 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 243 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 244 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 245 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 246 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 247 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 248 #endif
 249
 250 /*
 251  * Serial Port
 252  */
 253 #ifndef CONFIG_LPUART
 254 #define CONFIG_SYS_NS16550_SERIAL
 255 #ifndef CONFIG_DM_SERIAL
 256 #define CONFIG_SYS_NS16550_REG_SIZE     1
 257 #endif
 258 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 259 #endif
 260
 261 /*
 262  * I2C
 263  */
 264
 265 /* GPIO */
 266
 267 /* EEPROM */
 268 #define CONFIG_SYS_I2C_EEPROM_NXID
 269 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 270
 271 /*
 272  * I2C bus multiplexer
 273  */
 274 #define I2C_MUX_PCA_ADDR_PRI            0x77
 275 #define I2C_MUX_CH_DEFAULT              0x8
 276 #define I2C_MUX_CH_CH7301               0xC
 277
 278 /*
 279  * MMC
 280  */
 281
 282 /*
 283  * eTSEC
 284  */
 285
 286 #ifdef CONFIG_TSEC_ENET
 287 #define CONFIG_MII_DEFAULT_TSEC         3
 288 #define CONFIG_TSEC1                    1
 289 #define CONFIG_TSEC1_NAME               "eTSEC1"
 290 #define CONFIG_TSEC2                    1
 291 #define CONFIG_TSEC2_NAME               "eTSEC2"
 292 #define CONFIG_TSEC3                    1
 293 #define CONFIG_TSEC3_NAME               "eTSEC3"
 294
 295 #define TSEC1_PHY_ADDR                  1
 296 #define TSEC2_PHY_ADDR                  2
 297 #define TSEC3_PHY_ADDR                  3
 298
 299 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 300 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 301 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 302
 303 #define TSEC1_PHYIDX                    0
 304 #define TSEC2_PHYIDX                    0
 305 #define TSEC3_PHYIDX                    0
 306
 307 #define CONFIG_FSL_SGMII_RISER          1
 308 #define SGMII_RISER_PHY_OFFSET          0x1b
 309
 310 #ifdef CONFIG_FSL_SGMII_RISER
 311 #define CONFIG_SYS_TBIPA_VALUE          8
 312 #endif
 313
 314 #endif
 315
 316 /* PCIe */
 317 #define CONFIG_PCIE1            /* PCIE controller 1 */
 318 #define CONFIG_PCIE2            /* PCIE controller 2 */
 319
 320 #ifdef CONFIG_PCI
 321 #define CONFIG_PCI_SCAN_SHOW
 322 #endif
 323
 324 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 325 #define CONFIG_LAYERSCAPE_NS_ACCESS
 326 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 327
 328 #define CONFIG_HWCONFIG
 329 #define HWCONFIG_BUFFER_SIZE            256
 330
 331 #define CONFIG_FSL_DEVICE_DISABLE
 332
 333 #ifdef CONFIG_LPUART
 334 #define CONFIG_EXTRA_ENV_SETTINGS       \
 335         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 336         "initrd_high=0xffffffff\0"      \
 337         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 338 #else
 339 #define CONFIG_EXTRA_ENV_SETTINGS       \
 340         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 341         "initrd_high=0xffffffff\0"      \
 342         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 343 #endif
 344
 345 /*
 346  * Miscellaneous configurable options
 347  */
 348 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 349
 350 #define CONFIG_LS102XA_STREAM_ID
 351
 352 /*
 353  * Environment
 354  */
 355
 356 #include <asm/fsl_secure_boot.h>
 357 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 358
 359 #endif