include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_DEEP_SLEEP
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #ifndef __ASSEMBLY__
  18 unsigned long get_board_sys_clk(void);
  19 #endif
  20
  21 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  22 #define CONFIG_SYS_CLK_FREQ             100000000
  23 #define CONFIG_QIXIS_I2C_ACCESS
  24 #else
  25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  26 #endif
  27
  28 #ifdef CONFIG_SD_BOOT
  29 #define CONFIG_SPL_MAX_SIZE             0x1a000
  30 #define CONFIG_SPL_STACK                0x1001d000
  31 #define CONFIG_SPL_PAD_TO               0x1c000
  32
  33 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  34                 CONFIG_SYS_MONITOR_LEN)
  35 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  36 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  37 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  38 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  39 #endif
  40
  41 #ifdef CONFIG_NAND_BOOT
  42 #define CONFIG_SPL_MAX_SIZE             0x1a000
  43 #define CONFIG_SPL_STACK                0x1001d000
  44 #define CONFIG_SPL_PAD_TO               0x1c000
  45
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  48 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  49
  50 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  51 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  52 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  53 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  54 #define CONFIG_SYS_MONITOR_LEN          0x80000
  55 #endif
  56
  57 #define SPD_EEPROM_ADDRESS              0x51
  58 #define CONFIG_SYS_SPD_BUS_NUM          0
  59
  60 #ifndef CONFIG_SYS_FSL_DDR4
  61 #define CONFIG_SYS_DDR_RAW_TIMING
  62 #endif
  63 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  64 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  65
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  68
  69 #ifdef CONFIG_DDR_ECC
  70 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  71 #endif
  72
  73 /*
  74  * IFC Definitions
  75  */
  76 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  77 #define CONFIG_SYS_FLASH_BASE           0x60000000
  78 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  79
  80 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  81 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  82                                 CSPR_PORT_SIZE_16 | \
  83                                 CSPR_MSEL_NOR | \
  84                                 CSPR_V)
  85 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  86 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  87                                 + 0x8000000) | \
  88                                 CSPR_PORT_SIZE_16 | \
  89                                 CSPR_MSEL_NOR | \
  90                                 CSPR_V)
  91 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  92
  93 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  94                                         CSOR_NOR_TRHZ_80)
  95 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  96                                         FTIM0_NOR_TEADC(0x5) | \
  97                                         FTIM0_NOR_TEAHC(0x5))
  98 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  99                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 100                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 101 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 102                                         FTIM2_NOR_TCH(0x4) | \
 103                                         FTIM2_NOR_TWPH(0xe) | \
 104                                         FTIM2_NOR_TWP(0x1c))
 105 #define CONFIG_SYS_NOR_FTIM3            0
 106
 107 #define CONFIG_SYS_FLASH_QUIET_TEST
 108 #define CONFIG_FLASH_SHOW_PROGRESS      45
 109 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 110 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 111
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 113 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 114 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 115 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 116
 117 #define CONFIG_SYS_FLASH_EMPTY_INFO
 118 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 119                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 120
 121 /*
 122  * NAND Flash Definitions
 123  */
 124
 125 #define CONFIG_SYS_NAND_BASE            0x7e800000
 126 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 127
 128 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 129
 130 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 131                                 | CSPR_PORT_SIZE_8      \
 132                                 | CSPR_MSEL_NAND        \
 133                                 | CSPR_V)
 134 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 135 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 136                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 137                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 138                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 139                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 140                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 141                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 142
 143 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 144                                         FTIM0_NAND_TWP(0x18)   | \
 145                                         FTIM0_NAND_TWCHT(0x7) | \
 146                                         FTIM0_NAND_TWH(0xa))
 147 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 148                                         FTIM1_NAND_TWBE(0x39)  | \
 149                                         FTIM1_NAND_TRR(0xe)   | \
 150                                         FTIM1_NAND_TRP(0x18))
 151 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 152                                         FTIM2_NAND_TREH(0xa) | \
 153                                         FTIM2_NAND_TWHRE(0x1e))
 154 #define CONFIG_SYS_NAND_FTIM3           0x0
 155
 156 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 157 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 158 #endif
 159
 160 /*
 161  * QIXIS Definitions
 162  */
 163 #define CONFIG_FSL_QIXIS
 164
 165 #ifdef CONFIG_FSL_QIXIS
 166 #define QIXIS_BASE                      0x7fb00000
 167 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 168 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 169 #define QIXIS_LBMAP_SWITCH              6
 170 #define QIXIS_LBMAP_MASK                0x0f
 171 #define QIXIS_LBMAP_SHIFT               0
 172 #define QIXIS_LBMAP_DFLTBANK            0x00
 173 #define QIXIS_LBMAP_ALTBANK             0x04
 174 #define QIXIS_PWR_CTL                   0x21
 175 #define QIXIS_PWR_CTL_POWEROFF          0x80
 176 #define QIXIS_RST_CTL_RESET             0x44
 177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 178 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 180 #define QIXIS_CTL_SYS                   0x5
 181 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 182 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 183 #define QIXIS_RST_FORCE_3               0x45
 184 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 185 #define QIXIS_PWR_CTL2                  0x21
 186 #define QIXIS_PWR_CTL2_PCTL             0x2
 187
 188 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 189 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 190                                         CSPR_PORT_SIZE_8 | \
 191                                         CSPR_MSEL_GPCM | \
 192                                         CSPR_V)
 193 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 194 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 195                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 196                                         CSOR_NOR_TRHZ_80)
 197
 198 /*
 199  * QIXIS Timing parameters for IFC GPCM
 200  */
 201 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 202                                         FTIM0_GPCM_TEADC(0xe) | \
 203                                         FTIM0_GPCM_TEAHC(0xe))
 204 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 205                                         FTIM1_GPCM_TRAD(0x1f))
 206 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 207                                         FTIM2_GPCM_TCH(0xe) | \
 208                                         FTIM2_GPCM_TWP(0xf0))
 209 #define CONFIG_SYS_FPGA_FTIM3           0x0
 210 #endif
 211
 212 #if defined(CONFIG_NAND_BOOT)
 213 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 214 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 215 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 216 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 217 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 218 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 219 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 220 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 221 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 222 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 223 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 224 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 225 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 226 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 227 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 228 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 229 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 230 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 231 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 232 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 233 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 234 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 235 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 236 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 237 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 238 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 239 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 240 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 241 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 242 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 243 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 244 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 245 #else
 246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 263 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 264 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 265 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 266 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 267 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 268 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 269 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 270 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 271 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 272 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 273 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 274 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 275 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 276 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 277 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 278 #endif
 279
 280 /*
 281  * Serial Port
 282  */
 283 #ifdef CONFIG_LPUART
 284 #define CONFIG_LPUART_32B_REG
 285 #else
 286 #define CONFIG_SYS_NS16550_SERIAL
 287 #ifndef CONFIG_DM_SERIAL
 288 #define CONFIG_SYS_NS16550_REG_SIZE     1
 289 #endif
 290 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 291 #endif
 292
 293 /*
 294  * I2C
 295  */
 296
 297 /* GPIO */
 298
 299 /* EEPROM */
 300 #define CONFIG_SYS_I2C_EEPROM_NXID
 301 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 302
 303 /*
 304  * I2C bus multiplexer
 305  */
 306 #define I2C_MUX_PCA_ADDR_PRI            0x77
 307 #define I2C_MUX_CH_DEFAULT              0x8
 308 #define I2C_MUX_CH_CH7301               0xC
 309
 310 /*
 311  * MMC
 312  */
 313
 314 /*
 315  * Video
 316  */
 317 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 318 #define CONFIG_VIDEO_LOGO
 319 #define CONFIG_VIDEO_BMP_LOGO
 320
 321 #define CONFIG_FSL_DIU_CH7301
 322 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 323 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 324 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 325 #endif
 326
 327 /*
 328  * eTSEC
 329  */
 330
 331 #ifdef CONFIG_TSEC_ENET
 332 #define CONFIG_MII_DEFAULT_TSEC         3
 333 #define CONFIG_TSEC1                    1
 334 #define CONFIG_TSEC1_NAME               "eTSEC1"
 335 #define CONFIG_TSEC2                    1
 336 #define CONFIG_TSEC2_NAME               "eTSEC2"
 337 #define CONFIG_TSEC3                    1
 338 #define CONFIG_TSEC3_NAME               "eTSEC3"
 339
 340 #define TSEC1_PHY_ADDR                  1
 341 #define TSEC2_PHY_ADDR                  2
 342 #define TSEC3_PHY_ADDR                  3
 343
 344 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 345 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 346 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 347
 348 #define TSEC1_PHYIDX                    0
 349 #define TSEC2_PHYIDX                    0
 350 #define TSEC3_PHYIDX                    0
 351
 352 #define CONFIG_ETHPRIME                 "eTSEC1"
 353
 354 #define CONFIG_HAS_ETH0
 355 #define CONFIG_HAS_ETH1
 356 #define CONFIG_HAS_ETH2
 357
 358 #define CONFIG_FSL_SGMII_RISER          1
 359 #define SGMII_RISER_PHY_OFFSET          0x1b
 360
 361 #ifdef CONFIG_FSL_SGMII_RISER
 362 #define CONFIG_SYS_TBIPA_VALUE          8
 363 #endif
 364
 365 #endif
 366
 367 /* PCIe */
 368 #define CONFIG_PCIE1            /* PCIE controller 1 */
 369 #define CONFIG_PCIE2            /* PCIE controller 2 */
 370
 371 #ifdef CONFIG_PCI
 372 #define CONFIG_PCI_SCAN_SHOW
 373 #endif
 374
 375 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 376 #define CONFIG_LAYERSCAPE_NS_ACCESS
 377 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 378 #define COUNTER_FREQUENCY               12500000
 379
 380 #define CONFIG_HWCONFIG
 381 #define HWCONFIG_BUFFER_SIZE            256
 382
 383 #define CONFIG_FSL_DEVICE_DISABLE
 384
 385 #ifdef CONFIG_LPUART
 386 #define CONFIG_EXTRA_ENV_SETTINGS       \
 387         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 388         "initrd_high=0xffffffff\0"      \
 389         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 390 #else
 391 #define CONFIG_EXTRA_ENV_SETTINGS       \
 392         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 393         "initrd_high=0xffffffff\0"      \
 394         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 395 #endif
 396
 397 /*
 398  * Miscellaneous configurable options
 399  */
 400 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 401
 402 #define CONFIG_LS102XA_STREAM_ID
 403
 404 #define CONFIG_SYS_INIT_SP_OFFSET \
 405         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 406 #define CONFIG_SYS_INIT_SP_ADDR \
 407         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 408
 409 #ifdef CONFIG_SPL_BUILD
 410 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 411 #else
 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 413 #endif
 414
 415 /*
 416  * Environment
 417  */
 418
 419 #include <asm/fsl_secure_boot.h>
 420 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 421
 422 #endif