1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
14 #define CONFIG_SPL_STACK 0x1001d000
16 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
17 CONFIG_SYS_MONITOR_LEN)
18 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
19 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
20 #define CONFIG_SYS_MONITOR_LEN 0xc0000
23 #ifdef CONFIG_NAND_BOOT
24 #define CONFIG_SPL_STACK 0x1001d000
26 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
27 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
28 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
31 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
32 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
33 #define CONFIG_SYS_MONITOR_LEN 0x80000
36 #define SPD_EEPROM_ADDRESS 0x51
37 #define CONFIG_SYS_SPD_BUS_NUM 0
39 #ifndef CONFIG_SYS_FSL_DDR4
40 #define CONFIG_SYS_DDR_RAW_TIMING
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
44 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
53 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
54 #define CONFIG_SYS_FLASH_BASE 0x60000000
55 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
57 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
58 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
62 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
63 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
68 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
70 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
72 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
73 FTIM0_NOR_TEADC(0x5) | \
75 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
76 FTIM1_NOR_TRAD_NOR(0x1a) | \
77 FTIM1_NOR_TSEQRAD_NOR(0x13))
78 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
79 FTIM2_NOR_TCH(0x4) | \
80 FTIM2_NOR_TWPH(0xe) | \
82 #define CONFIG_SYS_NOR_FTIM3 0
84 #define CONFIG_SYS_FLASH_QUIET_TEST
85 #define CONFIG_FLASH_SHOW_PROGRESS 45
86 #define CONFIG_SYS_WRITE_SWAPPED_DATA
88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
92 #define CONFIG_SYS_FLASH_EMPTY_INFO
93 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
94 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
97 * NAND Flash Definitions
100 #define CONFIG_SYS_NAND_BASE 0x7e800000
101 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
103 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
105 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
109 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
110 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
111 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
112 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
113 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
114 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
115 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
116 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
118 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
119 FTIM0_NAND_TWP(0x18) | \
120 FTIM0_NAND_TWCHT(0x7) | \
122 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
123 FTIM1_NAND_TWBE(0x39) | \
124 FTIM1_NAND_TRR(0xe) | \
125 FTIM1_NAND_TRP(0x18))
126 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
127 FTIM2_NAND_TREH(0xa) | \
128 FTIM2_NAND_TWHRE(0x1e))
129 #define CONFIG_SYS_NAND_FTIM3 0x0
131 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1
139 #ifdef CONFIG_FSL_QIXIS
140 #define QIXIS_BASE 0x7fb00000
141 #define QIXIS_BASE_PHYS QIXIS_BASE
142 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
143 #define QIXIS_LBMAP_SWITCH 6
144 #define QIXIS_LBMAP_MASK 0x0f
145 #define QIXIS_LBMAP_SHIFT 0
146 #define QIXIS_LBMAP_DFLTBANK 0x00
147 #define QIXIS_LBMAP_ALTBANK 0x04
148 #define QIXIS_PWR_CTL 0x21
149 #define QIXIS_PWR_CTL_POWEROFF 0x80
150 #define QIXIS_RST_CTL_RESET 0x44
151 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
152 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
153 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
154 #define QIXIS_CTL_SYS 0x5
155 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
156 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
157 #define QIXIS_RST_FORCE_3 0x45
158 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
159 #define QIXIS_PWR_CTL2 0x21
160 #define QIXIS_PWR_CTL2_PCTL 0x2
162 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
163 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
167 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
168 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
169 CSOR_NOR_NOR_MODE_AVD_NOR | \
173 * QIXIS Timing parameters for IFC GPCM
175 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
176 FTIM0_GPCM_TEADC(0xe) | \
177 FTIM0_GPCM_TEAHC(0xe))
178 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
179 FTIM1_GPCM_TRAD(0x1f))
180 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
181 FTIM2_GPCM_TCH(0xe) | \
182 FTIM2_GPCM_TWP(0xf0))
183 #define CONFIG_SYS_FPGA_FTIM3 0x0
186 #if defined(CONFIG_NAND_BOOT)
187 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
188 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
189 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
190 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
191 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
192 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
193 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
194 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
195 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
196 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
198 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
199 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
200 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
201 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
202 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
203 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
204 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
205 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
206 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
207 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
208 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
209 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
210 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
211 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
212 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
213 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
214 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
215 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
216 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
217 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
218 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
220 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
221 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
222 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
223 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
224 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
225 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
226 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
228 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
229 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
230 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
231 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
232 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
233 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
234 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
235 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
236 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
237 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
238 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
239 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
240 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
241 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
242 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
243 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
244 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
245 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
246 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
247 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
248 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
249 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
250 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
251 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
257 #ifndef CONFIG_LPUART
258 #define CONFIG_SYS_NS16550_SERIAL
259 #ifndef CONFIG_DM_SERIAL
260 #define CONFIG_SYS_NS16550_REG_SIZE 1
262 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
272 #define CONFIG_SYS_I2C_EEPROM_NXID
273 #define CONFIG_SYS_EEPROM_BUS_NUM 0
276 * I2C bus multiplexer
278 #define I2C_MUX_PCA_ADDR_PRI 0x77
279 #define I2C_MUX_CH_DEFAULT 0x8
280 #define I2C_MUX_CH_CH7301 0xC
290 #ifdef CONFIG_TSEC_ENET
291 #define CONFIG_MII_DEFAULT_TSEC 3
292 #define CONFIG_TSEC1 1
293 #define CONFIG_TSEC1_NAME "eTSEC1"
294 #define CONFIG_TSEC2 1
295 #define CONFIG_TSEC2_NAME "eTSEC2"
296 #define CONFIG_TSEC3 1
297 #define CONFIG_TSEC3_NAME "eTSEC3"
299 #define TSEC1_PHY_ADDR 1
300 #define TSEC2_PHY_ADDR 2
301 #define TSEC3_PHY_ADDR 3
303 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
304 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
305 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
307 #define TSEC1_PHYIDX 0
308 #define TSEC2_PHYIDX 0
309 #define TSEC3_PHYIDX 0
311 #define CONFIG_FSL_SGMII_RISER 1
312 #define SGMII_RISER_PHY_OFFSET 0x1b
314 #ifdef CONFIG_FSL_SGMII_RISER
315 #define CONFIG_SYS_TBIPA_VALUE 8
321 #define CONFIG_PCIE1 /* PCIE controller 1 */
322 #define CONFIG_PCIE2 /* PCIE controller 2 */
325 #define CONFIG_PCI_SCAN_SHOW
328 #define CONFIG_PEN_ADDR_BIG_ENDIAN
329 #define CONFIG_LAYERSCAPE_NS_ACCESS
330 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
332 #define CONFIG_HWCONFIG
333 #define HWCONFIG_BUFFER_SIZE 256
335 #define CONFIG_FSL_DEVICE_DISABLE
338 #define CONFIG_EXTRA_ENV_SETTINGS \
339 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
340 "initrd_high=0xffffffff\0" \
341 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
343 #define CONFIG_EXTRA_ENV_SETTINGS \
344 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
345 "initrd_high=0xffffffff\0" \
346 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
350 * Miscellaneous configurable options
352 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
354 #define CONFIG_LS102XA_STREAM_ID
360 #include <asm/fsl_secure_boot.h>
361 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */