1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_DEEP_SLEEP
14 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
15 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
17 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
18 #define CONFIG_QIXIS_I2C_ACCESS
22 #define CONFIG_SPL_MAX_SIZE 0x1a000
23 #define CONFIG_SPL_STACK 0x1001d000
24 #define CONFIG_SPL_PAD_TO 0x1c000
26 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
27 CONFIG_SYS_MONITOR_LEN)
28 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
29 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
30 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
31 #define CONFIG_SYS_MONITOR_LEN 0xc0000
34 #ifdef CONFIG_NAND_BOOT
35 #define CONFIG_SPL_MAX_SIZE 0x1a000
36 #define CONFIG_SPL_STACK 0x1001d000
37 #define CONFIG_SPL_PAD_TO 0x1c000
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
40 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
44 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
45 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
46 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
47 #define CONFIG_SYS_MONITOR_LEN 0x80000
50 #define SPD_EEPROM_ADDRESS 0x51
51 #define CONFIG_SYS_SPD_BUS_NUM 0
53 #ifndef CONFIG_SYS_FSL_DDR4
54 #define CONFIG_SYS_DDR_RAW_TIMING
56 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
57 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
63 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
69 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
70 #define CONFIG_SYS_FLASH_BASE 0x60000000
71 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
73 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
74 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
78 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
79 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
84 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
86 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
88 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
89 FTIM0_NOR_TEADC(0x5) | \
91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
92 FTIM1_NOR_TRAD_NOR(0x1a) | \
93 FTIM1_NOR_TSEQRAD_NOR(0x13))
94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
95 FTIM2_NOR_TCH(0x4) | \
96 FTIM2_NOR_TWPH(0xe) | \
98 #define CONFIG_SYS_NOR_FTIM3 0
100 #define CONFIG_SYS_FLASH_QUIET_TEST
101 #define CONFIG_FLASH_SHOW_PROGRESS 45
102 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
103 #define CONFIG_SYS_WRITE_SWAPPED_DATA
105 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
109 #define CONFIG_SYS_FLASH_EMPTY_INFO
110 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
111 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
114 * NAND Flash Definitions
117 #define CONFIG_SYS_NAND_BASE 0x7e800000
118 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
120 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
122 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
126 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
127 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
128 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
129 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
130 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
131 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
132 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
133 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
135 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
136 FTIM0_NAND_TWP(0x18) | \
137 FTIM0_NAND_TWCHT(0x7) | \
139 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
140 FTIM1_NAND_TWBE(0x39) | \
141 FTIM1_NAND_TRR(0xe) | \
142 FTIM1_NAND_TRP(0x18))
143 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
144 FTIM2_NAND_TREH(0xa) | \
145 FTIM2_NAND_TWHRE(0x1e))
146 #define CONFIG_SYS_NAND_FTIM3 0x0
148 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
149 #define CONFIG_SYS_MAX_NAND_DEVICE 1
155 #define CONFIG_FSL_QIXIS
157 #ifdef CONFIG_FSL_QIXIS
158 #define QIXIS_BASE 0x7fb00000
159 #define QIXIS_BASE_PHYS QIXIS_BASE
160 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
161 #define QIXIS_LBMAP_SWITCH 6
162 #define QIXIS_LBMAP_MASK 0x0f
163 #define QIXIS_LBMAP_SHIFT 0
164 #define QIXIS_LBMAP_DFLTBANK 0x00
165 #define QIXIS_LBMAP_ALTBANK 0x04
166 #define QIXIS_PWR_CTL 0x21
167 #define QIXIS_PWR_CTL_POWEROFF 0x80
168 #define QIXIS_RST_CTL_RESET 0x44
169 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
170 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
171 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
172 #define QIXIS_CTL_SYS 0x5
173 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
174 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
175 #define QIXIS_RST_FORCE_3 0x45
176 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
177 #define QIXIS_PWR_CTL2 0x21
178 #define QIXIS_PWR_CTL2_PCTL 0x2
180 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
181 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
185 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
186 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
187 CSOR_NOR_NOR_MODE_AVD_NOR | \
191 * QIXIS Timing parameters for IFC GPCM
193 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
194 FTIM0_GPCM_TEADC(0xe) | \
195 FTIM0_GPCM_TEAHC(0xe))
196 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
197 FTIM1_GPCM_TRAD(0x1f))
198 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
199 FTIM2_GPCM_TCH(0xe) | \
200 FTIM2_GPCM_TWP(0xf0))
201 #define CONFIG_SYS_FPGA_FTIM3 0x0
204 #if defined(CONFIG_NAND_BOOT)
205 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
206 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
207 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
208 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
209 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
210 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
211 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
212 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
213 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
214 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
215 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
216 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
217 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
218 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
219 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
220 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
221 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
222 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
223 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
224 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
225 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
226 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
227 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
228 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
229 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
230 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
231 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
232 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
233 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
234 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
235 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
236 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
247 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
248 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
249 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
254 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
263 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
264 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
265 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
266 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
267 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
268 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
269 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
276 #define CONFIG_LPUART_32B_REG
278 #define CONFIG_SYS_NS16550_SERIAL
279 #ifndef CONFIG_DM_SERIAL
280 #define CONFIG_SYS_NS16550_REG_SIZE 1
282 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
292 #define CONFIG_SYS_I2C_EEPROM_NXID
293 #define CONFIG_SYS_EEPROM_BUS_NUM 0
296 * I2C bus multiplexer
298 #define I2C_MUX_PCA_ADDR_PRI 0x77
299 #define I2C_MUX_CH_DEFAULT 0x8
300 #define I2C_MUX_CH_CH7301 0xC
309 #ifdef CONFIG_VIDEO_FSL_DCU_FB
310 #define CONFIG_VIDEO_BMP_LOGO
312 #define CONFIG_FSL_DIU_CH7301
313 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
314 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
315 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
322 #ifdef CONFIG_TSEC_ENET
323 #define CONFIG_MII_DEFAULT_TSEC 3
324 #define CONFIG_TSEC1 1
325 #define CONFIG_TSEC1_NAME "eTSEC1"
326 #define CONFIG_TSEC2 1
327 #define CONFIG_TSEC2_NAME "eTSEC2"
328 #define CONFIG_TSEC3 1
329 #define CONFIG_TSEC3_NAME "eTSEC3"
331 #define TSEC1_PHY_ADDR 1
332 #define TSEC2_PHY_ADDR 2
333 #define TSEC3_PHY_ADDR 3
335 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
337 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
339 #define TSEC1_PHYIDX 0
340 #define TSEC2_PHYIDX 0
341 #define TSEC3_PHYIDX 0
343 #define CONFIG_ETHPRIME "eTSEC1"
345 #define CONFIG_HAS_ETH0
346 #define CONFIG_HAS_ETH1
347 #define CONFIG_HAS_ETH2
349 #define CONFIG_FSL_SGMII_RISER 1
350 #define SGMII_RISER_PHY_OFFSET 0x1b
352 #ifdef CONFIG_FSL_SGMII_RISER
353 #define CONFIG_SYS_TBIPA_VALUE 8
359 #define CONFIG_PCIE1 /* PCIE controller 1 */
360 #define CONFIG_PCIE2 /* PCIE controller 2 */
363 #define CONFIG_PCI_SCAN_SHOW
366 #define CONFIG_PEN_ADDR_BIG_ENDIAN
367 #define CONFIG_LAYERSCAPE_NS_ACCESS
368 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
369 #define COUNTER_FREQUENCY 12500000
371 #define CONFIG_HWCONFIG
372 #define HWCONFIG_BUFFER_SIZE 256
374 #define CONFIG_FSL_DEVICE_DISABLE
377 #define CONFIG_EXTRA_ENV_SETTINGS \
378 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
379 "initrd_high=0xffffffff\0" \
380 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
382 #define CONFIG_EXTRA_ENV_SETTINGS \
383 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
384 "initrd_high=0xffffffff\0" \
385 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
389 * Miscellaneous configurable options
391 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
393 #define CONFIG_LS102XA_STREAM_ID
395 #define CONFIG_SYS_INIT_SP_OFFSET \
396 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
397 #define CONFIG_SYS_INIT_SP_ADDR \
398 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
400 #ifdef CONFIG_SPL_BUILD
401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
410 #include <asm/fsl_secure_boot.h>
411 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */