2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_SYS_GENERIC_BOARD
14 #define CONFIG_DISPLAY_CPUINFO
15 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_SKIP_LOWLEVEL_INIT
18 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_DEEP_SLEEP
21 #if defined(CONFIG_DEEP_SLEEP)
22 #define CONFIG_SILENT_CONSOLE
26 * Size of malloc() pool
28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
31 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
34 * Generic Timer Definitions
36 #define GENERIC_TIMER_CLK 12500000
39 unsigned long get_board_sys_clk(void);
40 unsigned long get_board_ddr_clk(void);
43 #ifdef CONFIG_QSPI_BOOT
44 #define CONFIG_SYS_CLK_FREQ 100000000
45 #define CONFIG_DDR_CLK_FREQ 100000000
46 #define CONFIG_QIXIS_I2C_ACCESS
48 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
49 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
52 #ifdef CONFIG_RAMBOOT_PBL
53 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
58 #define CONFIG_SPL_FRAMEWORK
59 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
60 #define CONFIG_SPL_LIBCOMMON_SUPPORT
61 #define CONFIG_SPL_LIBGENERIC_SUPPORT
62 #define CONFIG_SPL_ENV_SUPPORT
63 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
64 #define CONFIG_SPL_I2C_SUPPORT
65 #define CONFIG_SPL_WATCHDOG_SUPPORT
66 #define CONFIG_SPL_SERIAL_SUPPORT
67 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
68 #define CONFIG_SPL_MMC_SUPPORT
69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
72 #define CONFIG_SPL_TEXT_BASE 0x10000000
73 #define CONFIG_SPL_MAX_SIZE 0x1a000
74 #define CONFIG_SPL_STACK 0x1001d000
75 #define CONFIG_SPL_PAD_TO 0x1c000
76 #define CONFIG_SYS_TEXT_BASE 0x82000000
78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
79 CONFIG_SYS_MONITOR_LEN)
80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
83 #define CONFIG_SYS_MONITOR_LEN 0x80000
86 #ifdef CONFIG_QSPI_BOOT
87 #define CONFIG_SYS_TEXT_BASE 0x40010000
88 #define CONFIG_SYS_NO_FLASH
91 #ifdef CONFIG_NAND_BOOT
92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
93 #define CONFIG_SPL_FRAMEWORK
94 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
95 #define CONFIG_SPL_LIBCOMMON_SUPPORT
96 #define CONFIG_SPL_LIBGENERIC_SUPPORT
97 #define CONFIG_SPL_ENV_SUPPORT
98 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
99 #define CONFIG_SPL_I2C_SUPPORT
100 #define CONFIG_SPL_WATCHDOG_SUPPORT
101 #define CONFIG_SPL_SERIAL_SUPPORT
102 #define CONFIG_SPL_NAND_SUPPORT
103 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
105 #define CONFIG_SPL_TEXT_BASE 0x10000000
106 #define CONFIG_SPL_MAX_SIZE 0x1a000
107 #define CONFIG_SPL_STACK 0x1001d000
108 #define CONFIG_SPL_PAD_TO 0x1c000
109 #define CONFIG_SYS_TEXT_BASE 0x82000000
111 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
112 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
113 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
114 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
117 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
118 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
119 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
120 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
121 #define CONFIG_SYS_MONITOR_LEN 0x80000
124 #ifndef CONFIG_SYS_TEXT_BASE
125 #define CONFIG_SYS_TEXT_BASE 0x60100000
128 #define CONFIG_NR_DRAM_BANKS 1
130 #define CONFIG_DDR_SPD
131 #define SPD_EEPROM_ADDRESS 0x51
132 #define CONFIG_SYS_SPD_BUS_NUM 0
134 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
135 #ifndef CONFIG_SYS_FSL_DDR4
136 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
137 #define CONFIG_SYS_DDR_RAW_TIMING
139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
140 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
142 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
143 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
145 #define CONFIG_DDR_ECC
146 #ifdef CONFIG_DDR_ECC
147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
148 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
151 #define CONFIG_SYS_HAS_SERDES
153 #define CONFIG_FSL_CAAM /* Enable CAAM */
155 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
156 !defined(CONFIG_QSPI_BOOT)
163 #ifndef CONFIG_QSPI_BOOT
164 #define CONFIG_FSL_IFC
165 #define CONFIG_SYS_FLASH_BASE 0x60000000
166 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
168 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
169 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
170 CSPR_PORT_SIZE_16 | \
173 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
174 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
176 CSPR_PORT_SIZE_16 | \
179 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
181 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
183 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
184 FTIM0_NOR_TEADC(0x5) | \
185 FTIM0_NOR_TEAHC(0x5))
186 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
187 FTIM1_NOR_TRAD_NOR(0x1a) | \
188 FTIM1_NOR_TSEQRAD_NOR(0x13))
189 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
190 FTIM2_NOR_TCH(0x4) | \
191 FTIM2_NOR_TWPH(0xe) | \
193 #define CONFIG_SYS_NOR_FTIM3 0
195 #define CONFIG_FLASH_CFI_DRIVER
196 #define CONFIG_SYS_FLASH_CFI
197 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45
200 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
201 #define CONFIG_SYS_WRITE_SWAPPED_DATA
203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
208 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
210 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
213 * NAND Flash Definitions
215 #define CONFIG_NAND_FSL_IFC
217 #define CONFIG_SYS_NAND_BASE 0x7e800000
218 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
220 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
222 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
227 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
228 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
229 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
230 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
231 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
232 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
233 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
235 #define CONFIG_SYS_NAND_ONFI_DETECTION
237 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
238 FTIM0_NAND_TWP(0x18) | \
239 FTIM0_NAND_TWCHT(0x7) | \
241 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
242 FTIM1_NAND_TWBE(0x39) | \
243 FTIM1_NAND_TRR(0xe) | \
244 FTIM1_NAND_TRP(0x18))
245 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
246 FTIM2_NAND_TREH(0xa) | \
247 FTIM2_NAND_TWHRE(0x1e))
248 #define CONFIG_SYS_NAND_FTIM3 0x0
250 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
251 #define CONFIG_SYS_MAX_NAND_DEVICE 1
252 #define CONFIG_CMD_NAND
254 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
260 #define CONFIG_FSL_QIXIS
262 #ifdef CONFIG_FSL_QIXIS
263 #define QIXIS_BASE 0x7fb00000
264 #define QIXIS_BASE_PHYS QIXIS_BASE
265 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
266 #define QIXIS_LBMAP_SWITCH 6
267 #define QIXIS_LBMAP_MASK 0x0f
268 #define QIXIS_LBMAP_SHIFT 0
269 #define QIXIS_LBMAP_DFLTBANK 0x00
270 #define QIXIS_LBMAP_ALTBANK 0x04
271 #define QIXIS_RST_CTL_RESET 0x44
272 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
273 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
274 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
276 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
277 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
281 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
282 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
283 CSOR_NOR_NOR_MODE_AVD_NOR | \
287 * QIXIS Timing parameters for IFC GPCM
289 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
290 FTIM0_GPCM_TEADC(0xe) | \
291 FTIM0_GPCM_TEAHC(0xe))
292 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
293 FTIM1_GPCM_TRAD(0x1f))
294 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
295 FTIM2_GPCM_TCH(0xe) | \
296 FTIM2_GPCM_TWP(0xf0))
297 #define CONFIG_SYS_FPGA_FTIM3 0x0
300 #if defined(CONFIG_NAND_BOOT)
301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
309 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
310 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
311 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
312 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
313 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
314 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
315 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
316 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
318 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
319 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
325 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
326 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
327 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
328 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
329 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
330 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
331 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
332 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
358 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
359 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
360 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
361 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
362 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
363 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
364 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
365 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
372 #define CONFIG_FSL_LPUART
373 #define CONFIG_LPUART_32B_REG
375 #define CONFIG_CONS_INDEX 1
376 #define CONFIG_SYS_NS16550
377 #define CONFIG_SYS_NS16550_SERIAL
378 #define CONFIG_SYS_NS16550_REG_SIZE 1
379 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
382 #define CONFIG_BAUDRATE 115200
387 #define CONFIG_CMD_I2C
388 #define CONFIG_SYS_I2C
389 #define CONFIG_SYS_I2C_MXC
390 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
393 * I2C bus multiplexer
395 #define I2C_MUX_PCA_ADDR_PRI 0x77
396 #define I2C_MUX_CH_DEFAULT 0x8
397 #define I2C_MUX_CH_CH7301 0xC
403 #define CONFIG_CMD_MMC
404 #define CONFIG_FSL_ESDHC
405 #define CONFIG_GENERIC_MMC
407 #define CONFIG_CMD_FAT
408 #define CONFIG_DOS_PARTITION
411 #ifdef CONFIG_QSPI_BOOT
413 #define CONFIG_FSL_QSPI
414 #define QSPI0_AMBA_BASE 0x40000000
415 #define FSL_QSPI_FLASH_SIZE (1 << 24)
416 #define FSL_QSPI_FLASH_NUM 2
417 #define CONFIG_SPI_FLASH_SPANSION
420 #define CONFIG_FSL_DSPI
423 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
424 #define CONFIG_CMD_SF
425 #define CONFIG_DM_SPI_FLASH
426 #define CONFIG_SPI_FLASH_DATAFLASH
433 #define CONFIG_HAS_FSL_DR_USB
435 #ifdef CONFIG_HAS_FSL_DR_USB
436 #define CONFIG_USB_EHCI
438 #ifdef CONFIG_USB_EHCI
439 #define CONFIG_CMD_USB
440 #define CONFIG_USB_STORAGE
441 #define CONFIG_USB_EHCI_FSL
442 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
443 #define CONFIG_CMD_EXT2
450 #define CONFIG_FSL_DCU_FB
452 #ifdef CONFIG_FSL_DCU_FB
454 #define CONFIG_CMD_BMP
455 #define CONFIG_CFB_CONSOLE
456 #define CONFIG_VGA_AS_SINGLE_DEVICE
457 #define CONFIG_VIDEO_LOGO
458 #define CONFIG_VIDEO_BMP_LOGO
460 #define CONFIG_FSL_DIU_CH7301
461 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
462 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
463 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
469 #define CONFIG_TSEC_ENET
471 #ifdef CONFIG_TSEC_ENET
473 #define CONFIG_MII_DEFAULT_TSEC 3
474 #define CONFIG_TSEC1 1
475 #define CONFIG_TSEC1_NAME "eTSEC1"
476 #define CONFIG_TSEC2 1
477 #define CONFIG_TSEC2_NAME "eTSEC2"
478 #define CONFIG_TSEC3 1
479 #define CONFIG_TSEC3_NAME "eTSEC3"
481 #define TSEC1_PHY_ADDR 1
482 #define TSEC2_PHY_ADDR 2
483 #define TSEC3_PHY_ADDR 3
485 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
486 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
489 #define TSEC1_PHYIDX 0
490 #define TSEC2_PHYIDX 0
491 #define TSEC3_PHYIDX 0
493 #define CONFIG_ETHPRIME "eTSEC1"
495 #define CONFIG_PHY_GIGE
496 #define CONFIG_PHYLIB
497 #define CONFIG_PHY_REALTEK
499 #define CONFIG_HAS_ETH0
500 #define CONFIG_HAS_ETH1
501 #define CONFIG_HAS_ETH2
503 #define CONFIG_FSL_SGMII_RISER 1
504 #define SGMII_RISER_PHY_OFFSET 0x1b
506 #ifdef CONFIG_FSL_SGMII_RISER
507 #define CONFIG_SYS_TBIPA_VALUE 8
513 #define CONFIG_PCI /* Enable PCI/PCIE */
514 #define CONFIG_PCIE1 /* PCIE controler 1 */
515 #define CONFIG_PCIE2 /* PCIE controler 2 */
516 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
517 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
519 #define CONFIG_SYS_PCI_64BIT
521 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
522 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
523 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
524 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
526 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
527 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
528 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
530 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
531 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
532 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
535 #define CONFIG_PCI_PNP
537 #define CONFIG_PCI_SCAN_SHOW
538 #define CONFIG_CMD_PCI
541 #define CONFIG_CMD_PING
542 #define CONFIG_CMD_DHCP
543 #define CONFIG_CMD_MII
545 #define CONFIG_CMDLINE_TAG
546 #define CONFIG_CMDLINE_EDITING
548 #define CONFIG_ARMV7_NONSEC
549 #define CONFIG_ARMV7_VIRT
550 #define CONFIG_PEN_ADDR_BIG_ENDIAN
551 #define CONFIG_LS102XA_NS_ACCESS
552 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
553 #define CONFIG_TIMER_CLK_FREQ 12500000
554 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
556 #define CONFIG_HWCONFIG
557 #define HWCONFIG_BUFFER_SIZE 128
559 #define CONFIG_BOOTDELAY 3
561 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
564 #define CONFIG_EXTRA_ENV_SETTINGS \
565 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
566 "fdt_high=0xcfffffff\0" \
567 "initrd_high=0xcfffffff\0" \
568 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
570 #define CONFIG_EXTRA_ENV_SETTINGS \
571 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
572 "fdt_high=0xcfffffff\0" \
573 "initrd_high=0xcfffffff\0" \
574 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
578 * Miscellaneous configurable options
580 #define CONFIG_SYS_LONGHELP /* undef to save memory */
581 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
582 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
583 #define CONFIG_AUTO_COMPLETE
584 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
585 #define CONFIG_SYS_PBSIZE \
586 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
587 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
588 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
590 #define CONFIG_CMD_GREPENV
591 #define CONFIG_CMD_MEMINFO
592 #define CONFIG_CMD_MEMTEST
593 #define CONFIG_SYS_MEMTEST_START 0x80000000
594 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
596 #define CONFIG_SYS_LOAD_ADDR 0x82000000
598 #define CONFIG_LS102XA_STREAM_ID
602 * The stack sizes are set up in start.S using the settings below
604 #define CONFIG_STACKSIZE (30 * 1024)
606 #define CONFIG_SYS_INIT_SP_OFFSET \
607 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
608 #define CONFIG_SYS_INIT_SP_ADDR \
609 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
611 #ifdef CONFIG_SPL_BUILD
612 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
614 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
620 #define CONFIG_ENV_OVERWRITE
622 #if defined(CONFIG_SD_BOOT)
623 #define CONFIG_ENV_OFFSET 0x100000
624 #define CONFIG_ENV_IS_IN_MMC
625 #define CONFIG_SYS_MMC_ENV_DEV 0
626 #define CONFIG_ENV_SIZE 0x2000
627 #elif defined(CONFIG_QSPI_BOOT)
628 #define CONFIG_ENV_IS_IN_SPI_FLASH
629 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
630 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
631 #define CONFIG_ENV_SECT_SIZE 0x10000
632 #elif defined(CONFIG_NAND_BOOT)
633 #define CONFIG_ENV_IS_IN_NAND
634 #define CONFIG_ENV_SIZE 0x2000
635 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
637 #define CONFIG_ENV_IS_IN_FLASH
638 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
639 #define CONFIG_ENV_SIZE 0x2000
640 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
643 #define CONFIG_OF_LIBFDT
644 #define CONFIG_OF_BOARD_SETUP
645 #define CONFIG_CMD_BOOTZ
647 #define CONFIG_MISC_INIT_R
649 /* Hash command with SHA acceleration supported in hardware */
650 #define CONFIG_CMD_HASH
651 #define CONFIG_SHA_HW_ACCEL
653 #ifdef CONFIG_SECURE_BOOT
654 #define CONFIG_CMD_BLOB
655 #include <asm/fsl_secure_boot.h>