include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DEEP_SLEEP
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  16 #define CONFIG_QIXIS_I2C_ACCESS
  17 #endif
  18
  19 #ifdef CONFIG_SD_BOOT
  20 #define CONFIG_SPL_MAX_SIZE             0x1a000
  21 #define CONFIG_SPL_STACK                0x1001d000
  22 #define CONFIG_SPL_PAD_TO               0x1c000
  23
  24 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  25                 CONFIG_SYS_MONITOR_LEN)
  26 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  27 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  28 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  29 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  30 #endif
  31
  32 #ifdef CONFIG_NAND_BOOT
  33 #define CONFIG_SPL_MAX_SIZE             0x1a000
  34 #define CONFIG_SPL_STACK                0x1001d000
  35 #define CONFIG_SPL_PAD_TO               0x1c000
  36
  37 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  38 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  39 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  40
  41 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  42 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  43 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  44 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  45 #define CONFIG_SYS_MONITOR_LEN          0x80000
  46 #endif
  47
  48 #define SPD_EEPROM_ADDRESS              0x51
  49 #define CONFIG_SYS_SPD_BUS_NUM          0
  50
  51 #ifndef CONFIG_SYS_FSL_DDR4
  52 #define CONFIG_SYS_DDR_RAW_TIMING
  53 #endif
  54 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  55
  56 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  58
  59 #ifdef CONFIG_DDR_ECC
  60 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  61 #endif
  62
  63 /*
  64  * IFC Definitions
  65  */
  66 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  67 #define CONFIG_SYS_FLASH_BASE           0x60000000
  68 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  69
  70 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  71 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  72                                 CSPR_PORT_SIZE_16 | \
  73                                 CSPR_MSEL_NOR | \
  74                                 CSPR_V)
  75 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  76 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  77                                 + 0x8000000) | \
  78                                 CSPR_PORT_SIZE_16 | \
  79                                 CSPR_MSEL_NOR | \
  80                                 CSPR_V)
  81 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  82
  83 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  84                                         CSOR_NOR_TRHZ_80)
  85 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  86                                         FTIM0_NOR_TEADC(0x5) | \
  87                                         FTIM0_NOR_TEAHC(0x5))
  88 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  89                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  90                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  91 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  92                                         FTIM2_NOR_TCH(0x4) | \
  93                                         FTIM2_NOR_TWPH(0xe) | \
  94                                         FTIM2_NOR_TWP(0x1c))
  95 #define CONFIG_SYS_NOR_FTIM3            0
  96
  97 #define CONFIG_SYS_FLASH_QUIET_TEST
  98 #define CONFIG_FLASH_SHOW_PROGRESS      45
  99 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 100
 101 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 102 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 103 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 104
 105 #define CONFIG_SYS_FLASH_EMPTY_INFO
 106 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 107                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 108
 109 /*
 110  * NAND Flash Definitions
 111  */
 112
 113 #define CONFIG_SYS_NAND_BASE            0x7e800000
 114 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 115
 116 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 117
 118 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 119                                 | CSPR_PORT_SIZE_8      \
 120                                 | CSPR_MSEL_NAND        \
 121                                 | CSPR_V)
 122 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 123 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 124                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 125                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 126                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 127                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 128                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 129                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 130
 131 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 132                                         FTIM0_NAND_TWP(0x18)   | \
 133                                         FTIM0_NAND_TWCHT(0x7) | \
 134                                         FTIM0_NAND_TWH(0xa))
 135 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 136                                         FTIM1_NAND_TWBE(0x39)  | \
 137                                         FTIM1_NAND_TRR(0xe)   | \
 138                                         FTIM1_NAND_TRP(0x18))
 139 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 140                                         FTIM2_NAND_TREH(0xa) | \
 141                                         FTIM2_NAND_TWHRE(0x1e))
 142 #define CONFIG_SYS_NAND_FTIM3           0x0
 143
 144 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 145 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 146 #endif
 147
 148 /*
 149  * QIXIS Definitions
 150  */
 151 #define CONFIG_FSL_QIXIS
 152
 153 #ifdef CONFIG_FSL_QIXIS
 154 #define QIXIS_BASE                      0x7fb00000
 155 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 156 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 157 #define QIXIS_LBMAP_SWITCH              6
 158 #define QIXIS_LBMAP_MASK                0x0f
 159 #define QIXIS_LBMAP_SHIFT               0
 160 #define QIXIS_LBMAP_DFLTBANK            0x00
 161 #define QIXIS_LBMAP_ALTBANK             0x04
 162 #define QIXIS_PWR_CTL                   0x21
 163 #define QIXIS_PWR_CTL_POWEROFF          0x80
 164 #define QIXIS_RST_CTL_RESET             0x44
 165 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 166 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 167 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 168 #define QIXIS_CTL_SYS                   0x5
 169 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 170 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 171 #define QIXIS_RST_FORCE_3               0x45
 172 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 173 #define QIXIS_PWR_CTL2                  0x21
 174 #define QIXIS_PWR_CTL2_PCTL             0x2
 175
 176 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 177 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 178                                         CSPR_PORT_SIZE_8 | \
 179                                         CSPR_MSEL_GPCM | \
 180                                         CSPR_V)
 181 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 182 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 183                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 184                                         CSOR_NOR_TRHZ_80)
 185
 186 /*
 187  * QIXIS Timing parameters for IFC GPCM
 188  */
 189 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 190                                         FTIM0_GPCM_TEADC(0xe) | \
 191                                         FTIM0_GPCM_TEAHC(0xe))
 192 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 193                                         FTIM1_GPCM_TRAD(0x1f))
 194 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 195                                         FTIM2_GPCM_TCH(0xe) | \
 196                                         FTIM2_GPCM_TWP(0xf0))
 197 #define CONFIG_SYS_FPGA_FTIM3           0x0
 198 #endif
 199
 200 #if defined(CONFIG_NAND_BOOT)
 201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 209 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 210 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 211 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 212 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 213 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 214 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 215 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 216 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 217 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 218 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 219 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 226 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 227 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 228 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 229 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 230 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 231 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 232 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 233 #else
 234 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 235 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 236 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 243 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 244 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 245 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 246 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 247 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 248 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 249 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 250 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 251 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 252 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 253 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 254 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 255 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 256 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 257 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 258 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 259 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 260 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 261 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 262 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 263 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 264 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 265 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 266 #endif
 267
 268 /*
 269  * Serial Port
 270  */
 271 #ifdef CONFIG_LPUART
 272 #define CONFIG_LPUART_32B_REG
 273 #else
 274 #define CONFIG_SYS_NS16550_SERIAL
 275 #ifndef CONFIG_DM_SERIAL
 276 #define CONFIG_SYS_NS16550_REG_SIZE     1
 277 #endif
 278 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 279 #endif
 280
 281 /*
 282  * I2C
 283  */
 284
 285 /* GPIO */
 286
 287 /* EEPROM */
 288 #define CONFIG_SYS_I2C_EEPROM_NXID
 289 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 290
 291 /*
 292  * I2C bus multiplexer
 293  */
 294 #define I2C_MUX_PCA_ADDR_PRI            0x77
 295 #define I2C_MUX_CH_DEFAULT              0x8
 296 #define I2C_MUX_CH_CH7301               0xC
 297
 298 /*
 299  * MMC
 300  */
 301
 302 /*
 303  * eTSEC
 304  */
 305
 306 #ifdef CONFIG_TSEC_ENET
 307 #define CONFIG_MII_DEFAULT_TSEC         3
 308 #define CONFIG_TSEC1                    1
 309 #define CONFIG_TSEC1_NAME               "eTSEC1"
 310 #define CONFIG_TSEC2                    1
 311 #define CONFIG_TSEC2_NAME               "eTSEC2"
 312 #define CONFIG_TSEC3                    1
 313 #define CONFIG_TSEC3_NAME               "eTSEC3"
 314
 315 #define TSEC1_PHY_ADDR                  1
 316 #define TSEC2_PHY_ADDR                  2
 317 #define TSEC3_PHY_ADDR                  3
 318
 319 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 320 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 321 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 322
 323 #define TSEC1_PHYIDX                    0
 324 #define TSEC2_PHYIDX                    0
 325 #define TSEC3_PHYIDX                    0
 326
 327 #define CONFIG_FSL_SGMII_RISER          1
 328 #define SGMII_RISER_PHY_OFFSET          0x1b
 329
 330 #ifdef CONFIG_FSL_SGMII_RISER
 331 #define CONFIG_SYS_TBIPA_VALUE          8
 332 #endif
 333
 334 #endif
 335
 336 /* PCIe */
 337 #define CONFIG_PCIE1            /* PCIE controller 1 */
 338 #define CONFIG_PCIE2            /* PCIE controller 2 */
 339
 340 #ifdef CONFIG_PCI
 341 #define CONFIG_PCI_SCAN_SHOW
 342 #endif
 343
 344 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 345 #define CONFIG_LAYERSCAPE_NS_ACCESS
 346 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 347 #define COUNTER_FREQUENCY               12500000
 348
 349 #define CONFIG_HWCONFIG
 350 #define HWCONFIG_BUFFER_SIZE            256
 351
 352 #define CONFIG_FSL_DEVICE_DISABLE
 353
 354 #ifdef CONFIG_LPUART
 355 #define CONFIG_EXTRA_ENV_SETTINGS       \
 356         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 357         "initrd_high=0xffffffff\0"      \
 358         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 359 #else
 360 #define CONFIG_EXTRA_ENV_SETTINGS       \
 361         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 362         "initrd_high=0xffffffff\0"      \
 363         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 364 #endif
 365
 366 /*
 367  * Miscellaneous configurable options
 368  */
 369 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 370
 371 #define CONFIG_LS102XA_STREAM_ID
 372
 373 #define CONFIG_SYS_INIT_SP_OFFSET \
 374         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 375 #define CONFIG_SYS_INIT_SP_ADDR \
 376         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 377
 378 #ifdef CONFIG_SPL_BUILD
 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 380 #else
 381 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 382 #endif
 383
 384 /*
 385  * Environment
 386  */
 387
 388 #include <asm/fsl_secure_boot.h>
 389 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 390
 391 #endif