include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #define CONFIG_ARMV7_PSCI_1_0
  10
  11 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  12
  13 #define CONFIG_SYS_FSL_CLK
  14
  15 #define CONFIG_SKIP_LOWLEVEL_INIT
  16
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 #ifndef __ASSEMBLY__
  28 unsigned long get_board_sys_clk(void);
  29 unsigned long get_board_ddr_clk(void);
  30 #endif
  31
  32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  33 #define CONFIG_SYS_CLK_FREQ             100000000
  34 #define CONFIG_DDR_CLK_FREQ             100000000
  35 #define CONFIG_QIXIS_I2C_ACCESS
  36 #else
  37 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  38 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  39 #endif
  40
  41 #ifdef CONFIG_RAMBOOT_PBL
  42 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  43 #endif
  44
  45 #ifdef CONFIG_SD_BOOT
  46 #ifdef CONFIG_SD_BOOT_QSPI
  47 #define CONFIG_SYS_FSL_PBL_RCW  \
  48         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  49 #else
  50 #define CONFIG_SYS_FSL_PBL_RCW  \
  51         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  52 #endif
  53
  54 #define CONFIG_SPL_MAX_SIZE             0x1a000
  55 #define CONFIG_SPL_STACK                0x1001d000
  56 #define CONFIG_SPL_PAD_TO               0x1c000
  57
  58 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  59                 CONFIG_SYS_MONITOR_LEN)
  60 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  61 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  62 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  63 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  64 #endif
  65
  66 #ifdef CONFIG_NAND_BOOT
  67 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  68
  69 #define CONFIG_SPL_MAX_SIZE             0x1a000
  70 #define CONFIG_SPL_STACK                0x1001d000
  71 #define CONFIG_SPL_PAD_TO               0x1c000
  72
  73 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  74 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  75 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  76 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  77 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  78
  79 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  80 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  81 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  82 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  83 #define CONFIG_SYS_MONITOR_LEN          0x80000
  84 #endif
  85
  86 #define CONFIG_DDR_SPD
  87 #define SPD_EEPROM_ADDRESS              0x51
  88 #define CONFIG_SYS_SPD_BUS_NUM          0
  89
  90 #ifndef CONFIG_SYS_FSL_DDR4
  91 #define CONFIG_SYS_DDR_RAW_TIMING
  92 #endif
  93 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  94 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  95
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_DDR_ECC
 100 #ifdef CONFIG_DDR_ECC
 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 102 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 103 #endif
 104
 105 /*
 106  * IFC Definitions
 107  */
 108 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 109 #define CONFIG_FSL_IFC
 110 #define CONFIG_SYS_FLASH_BASE           0x60000000
 111 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 112
 113 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 114 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 115                                 CSPR_PORT_SIZE_16 | \
 116                                 CSPR_MSEL_NOR | \
 117                                 CSPR_V)
 118 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 119 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 120                                 + 0x8000000) | \
 121                                 CSPR_PORT_SIZE_16 | \
 122                                 CSPR_MSEL_NOR | \
 123                                 CSPR_V)
 124 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 125
 126 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 127                                         CSOR_NOR_TRHZ_80)
 128 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 129                                         FTIM0_NOR_TEADC(0x5) | \
 130                                         FTIM0_NOR_TEAHC(0x5))
 131 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 132                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 133                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 134 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 135                                         FTIM2_NOR_TCH(0x4) | \
 136                                         FTIM2_NOR_TWPH(0xe) | \
 137                                         FTIM2_NOR_TWP(0x1c))
 138 #define CONFIG_SYS_NOR_FTIM3            0
 139
 140 #define CONFIG_SYS_FLASH_QUIET_TEST
 141 #define CONFIG_FLASH_SHOW_PROGRESS      45
 142 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 143 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 144
 145 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 146 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 149
 150 #define CONFIG_SYS_FLASH_EMPTY_INFO
 151 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 152                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 153
 154 /*
 155  * NAND Flash Definitions
 156  */
 157 #define CONFIG_NAND_FSL_IFC
 158
 159 #define CONFIG_SYS_NAND_BASE            0x7e800000
 160 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 161
 162 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 163
 164 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 165                                 | CSPR_PORT_SIZE_8      \
 166                                 | CSPR_MSEL_NAND        \
 167                                 | CSPR_V)
 168 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 169 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 170                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 171                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 172                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 173                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 174                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 175                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 176
 177 #define CONFIG_SYS_NAND_ONFI_DETECTION
 178
 179 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 180                                         FTIM0_NAND_TWP(0x18)   | \
 181                                         FTIM0_NAND_TWCHT(0x7) | \
 182                                         FTIM0_NAND_TWH(0xa))
 183 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 184                                         FTIM1_NAND_TWBE(0x39)  | \
 185                                         FTIM1_NAND_TRR(0xe)   | \
 186                                         FTIM1_NAND_TRP(0x18))
 187 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 188                                         FTIM2_NAND_TREH(0xa) | \
 189                                         FTIM2_NAND_TWHRE(0x1e))
 190 #define CONFIG_SYS_NAND_FTIM3           0x0
 191
 192 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 193 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 194
 195 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 196 #endif
 197
 198 /*
 199  * QIXIS Definitions
 200  */
 201 #define CONFIG_FSL_QIXIS
 202
 203 #ifdef CONFIG_FSL_QIXIS
 204 #define QIXIS_BASE                      0x7fb00000
 205 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 206 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 207 #define QIXIS_LBMAP_SWITCH              6
 208 #define QIXIS_LBMAP_MASK                0x0f
 209 #define QIXIS_LBMAP_SHIFT               0
 210 #define QIXIS_LBMAP_DFLTBANK            0x00
 211 #define QIXIS_LBMAP_ALTBANK             0x04
 212 #define QIXIS_PWR_CTL                   0x21
 213 #define QIXIS_PWR_CTL_POWEROFF          0x80
 214 #define QIXIS_RST_CTL_RESET             0x44
 215 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 216 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 217 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 218 #define QIXIS_CTL_SYS                   0x5
 219 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 220 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 221 #define QIXIS_RST_FORCE_3               0x45
 222 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 223 #define QIXIS_PWR_CTL2                  0x21
 224 #define QIXIS_PWR_CTL2_PCTL             0x2
 225
 226 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 227 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 228                                         CSPR_PORT_SIZE_8 | \
 229                                         CSPR_MSEL_GPCM | \
 230                                         CSPR_V)
 231 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 232 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 233                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 234                                         CSOR_NOR_TRHZ_80)
 235
 236 /*
 237  * QIXIS Timing parameters for IFC GPCM
 238  */
 239 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 240                                         FTIM0_GPCM_TEADC(0xe) | \
 241                                         FTIM0_GPCM_TEAHC(0xe))
 242 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 243                                         FTIM1_GPCM_TRAD(0x1f))
 244 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 245                                         FTIM2_GPCM_TCH(0xe) | \
 246                                         FTIM2_GPCM_TWP(0xf0))
 247 #define CONFIG_SYS_FPGA_FTIM3           0x0
 248 #endif
 249
 250 #if defined(CONFIG_NAND_BOOT)
 251 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 252 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 253 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 254 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 255 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 256 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 257 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 258 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 259 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 260 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 261 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 262 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 263 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 264 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 265 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 266 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 267 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 268 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 269 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 270 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 271 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 272 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 273 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 274 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 275 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 276 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 277 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 278 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 279 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 280 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 281 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 282 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 283 #else
 284 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 285 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 286 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 287 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 288 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 289 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 290 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 291 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 292 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 293 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 294 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 295 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 296 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 297 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 298 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 299 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 300 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 301 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 302 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 303 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 304 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 305 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 306 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 307 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 308 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 309 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 310 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 311 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 312 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 313 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 314 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 315 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 316 #endif
 317
 318 /*
 319  * Serial Port
 320  */
 321 #ifdef CONFIG_LPUART
 322 #define CONFIG_LPUART_32B_REG
 323 #else
 324 #define CONFIG_SYS_NS16550_SERIAL
 325 #ifndef CONFIG_DM_SERIAL
 326 #define CONFIG_SYS_NS16550_REG_SIZE     1
 327 #endif
 328 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 329 #endif
 330
 331 /*
 332  * I2C
 333  */
 334 #define CONFIG_SYS_I2C
 335 #define CONFIG_SYS_I2C_MXC
 336 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 337 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 338 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 339
 340 /* EEPROM */
 341 #define CONFIG_ID_EEPROM
 342 #define CONFIG_SYS_I2C_EEPROM_NXID
 343 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 344 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 345 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 346 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 347 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 348
 349 /*
 350  * I2C bus multiplexer
 351  */
 352 #define I2C_MUX_PCA_ADDR_PRI            0x77
 353 #define I2C_MUX_CH_DEFAULT              0x8
 354 #define I2C_MUX_CH_CH7301               0xC
 355
 356 /*
 357  * MMC
 358  */
 359
 360 /* SPI */
 361 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 362 /* QSPI */
 363 #define QSPI0_AMBA_BASE                 0x40000000
 364 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 365 #define FSL_QSPI_FLASH_NUM              2
 366
 367 /* DSPI */
 368
 369 /* DM SPI */
 370 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 371 #define CONFIG_DM_SPI_FLASH
 372 #define CONFIG_SPI_FLASH_DATAFLASH
 373 #endif
 374 #endif
 375
 376 /*
 377  * Video
 378  */
 379 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 380 #define CONFIG_VIDEO_LOGO
 381 #define CONFIG_VIDEO_BMP_LOGO
 382
 383 #define CONFIG_FSL_DIU_CH7301
 384 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 385 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 386 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 387 #endif
 388
 389 /*
 390  * eTSEC
 391  */
 392
 393 #ifdef CONFIG_TSEC_ENET
 394 #define CONFIG_MII_DEFAULT_TSEC         3
 395 #define CONFIG_TSEC1                    1
 396 #define CONFIG_TSEC1_NAME               "eTSEC1"
 397 #define CONFIG_TSEC2                    1
 398 #define CONFIG_TSEC2_NAME               "eTSEC2"
 399 #define CONFIG_TSEC3                    1
 400 #define CONFIG_TSEC3_NAME               "eTSEC3"
 401
 402 #define TSEC1_PHY_ADDR                  1
 403 #define TSEC2_PHY_ADDR                  2
 404 #define TSEC3_PHY_ADDR                  3
 405
 406 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 407 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 408 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 409
 410 #define TSEC1_PHYIDX                    0
 411 #define TSEC2_PHYIDX                    0
 412 #define TSEC3_PHYIDX                    0
 413
 414 #define CONFIG_ETHPRIME                 "eTSEC1"
 415
 416 #define CONFIG_PHY_REALTEK
 417
 418 #define CONFIG_HAS_ETH0
 419 #define CONFIG_HAS_ETH1
 420 #define CONFIG_HAS_ETH2
 421
 422 #define CONFIG_FSL_SGMII_RISER          1
 423 #define SGMII_RISER_PHY_OFFSET          0x1b
 424
 425 #ifdef CONFIG_FSL_SGMII_RISER
 426 #define CONFIG_SYS_TBIPA_VALUE          8
 427 #endif
 428
 429 #endif
 430
 431 /* PCIe */
 432 #define CONFIG_PCIE1            /* PCIE controller 1 */
 433 #define CONFIG_PCIE2            /* PCIE controller 2 */
 434
 435 #ifdef CONFIG_PCI
 436 #define CONFIG_PCI_SCAN_SHOW
 437 #endif
 438
 439 #define CONFIG_CMDLINE_TAG
 440
 441 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 442 #define CONFIG_LAYERSCAPE_NS_ACCESS
 443 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 444 #define COUNTER_FREQUENCY               12500000
 445
 446 #define CONFIG_HWCONFIG
 447 #define HWCONFIG_BUFFER_SIZE            256
 448
 449 #define CONFIG_FSL_DEVICE_DISABLE
 450
 451
 452 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 453
 454 #ifdef CONFIG_LPUART
 455 #define CONFIG_EXTRA_ENV_SETTINGS       \
 456         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 457         "fdt_high=0xffffffff\0"         \
 458         "initrd_high=0xffffffff\0"      \
 459         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 460 #else
 461 #define CONFIG_EXTRA_ENV_SETTINGS       \
 462         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 463         "fdt_high=0xffffffff\0"         \
 464         "initrd_high=0xffffffff\0"      \
 465         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 466 #endif
 467
 468 /*
 469  * Miscellaneous configurable options
 470  */
 471
 472 #define CONFIG_SYS_MEMTEST_START        0x80000000
 473 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 474
 475 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 476
 477 #define CONFIG_LS102XA_STREAM_ID
 478
 479 #define CONFIG_SYS_INIT_SP_OFFSET \
 480         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 481 #define CONFIG_SYS_INIT_SP_ADDR \
 482         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 483
 484 #ifdef CONFIG_SPL_BUILD
 485 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 486 #else
 487 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 488 #endif
 489
 490 /*
 491  * Environment
 492  */
 493 #define CONFIG_ENV_OVERWRITE
 494
 495 #if defined(CONFIG_SD_BOOT)
 496 #define CONFIG_ENV_OFFSET               0x300000
 497 #define CONFIG_SYS_MMC_ENV_DEV          0
 498 #define CONFIG_ENV_SIZE                 0x2000
 499 #elif defined(CONFIG_QSPI_BOOT)
 500 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 501 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 502 #define CONFIG_ENV_SECT_SIZE            0x10000
 503 #elif defined(CONFIG_NAND_BOOT)
 504 #define CONFIG_ENV_SIZE                 0x2000
 505 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 506 #else
 507 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 508 #define CONFIG_ENV_SIZE                 0x2000
 509 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 510 #endif
 511
 512 #include <asm/fsl_secure_boot.h>
 513 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 514
 515 #endif