Merge git://git.denx.de/u-boot-mpc85xx
[platform/kernel/u-boot.git] / include / configs / ls1021aqds.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_LS102XA
11
12 #define CONFIG_ARMV7_PSCI_1_0
13
14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
15
16 #define CONFIG_SYS_FSL_CLK
17
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19
20 #define CONFIG_DEEP_SLEEP
21
22 /*
23  * Size of malloc() pool
24  */
25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
29
30 /*
31  * Generic Timer Definitions
32  */
33 #define GENERIC_TIMER_CLK               12500000
34
35 #ifndef __ASSEMBLY__
36 unsigned long get_board_sys_clk(void);
37 unsigned long get_board_ddr_clk(void);
38 #endif
39
40 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
41 #define CONFIG_SYS_CLK_FREQ             100000000
42 #define CONFIG_DDR_CLK_FREQ             100000000
43 #define CONFIG_QIXIS_I2C_ACCESS
44 #else
45 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
46 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
47 #endif
48
49 #ifdef CONFIG_RAMBOOT_PBL
50 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
51 #endif
52
53 #ifdef CONFIG_SD_BOOT
54 #ifdef CONFIG_SD_BOOT_QSPI
55 #define CONFIG_SYS_FSL_PBL_RCW  \
56         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
57 #else
58 #define CONFIG_SYS_FSL_PBL_RCW  \
59         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
60 #endif
61 #define CONFIG_SPL_FRAMEWORK
62 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
63
64 #define CONFIG_SPL_TEXT_BASE            0x10000000
65 #define CONFIG_SPL_MAX_SIZE             0x1a000
66 #define CONFIG_SPL_STACK                0x1001d000
67 #define CONFIG_SPL_PAD_TO               0x1c000
68 #define CONFIG_SYS_TEXT_BASE            0x82000000
69
70 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
71                 CONFIG_SYS_MONITOR_LEN)
72 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
73 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
74 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
75 #define CONFIG_SYS_MONITOR_LEN          0xc0000
76 #endif
77
78 #ifdef CONFIG_QSPI_BOOT
79 #define CONFIG_SYS_TEXT_BASE            0x40010000
80 #endif
81
82 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
83 #define CONFIG_SYS_NO_FLASH
84 #endif
85
86 #ifdef CONFIG_NAND_BOOT
87 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
88 #define CONFIG_SPL_FRAMEWORK
89 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
90
91 #define CONFIG_SPL_TEXT_BASE            0x10000000
92 #define CONFIG_SPL_MAX_SIZE             0x1a000
93 #define CONFIG_SPL_STACK                0x1001d000
94 #define CONFIG_SPL_PAD_TO               0x1c000
95 #define CONFIG_SYS_TEXT_BASE            0x82000000
96
97 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
98 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
99 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
100 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
101 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
102
103 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
104 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
105 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
106 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
107 #define CONFIG_SYS_MONITOR_LEN          0x80000
108 #endif
109
110 #ifndef CONFIG_SYS_TEXT_BASE
111 #define CONFIG_SYS_TEXT_BASE            0x60100000
112 #endif
113
114 #define CONFIG_NR_DRAM_BANKS            1
115
116 #define CONFIG_DDR_SPD
117 #define SPD_EEPROM_ADDRESS              0x51
118 #define CONFIG_SYS_SPD_BUS_NUM          0
119
120 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
121 #ifndef CONFIG_SYS_FSL_DDR4
122 #define CONFIG_SYS_DDR_RAW_TIMING
123 #endif
124 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
125 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
126
127 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
129
130 #define CONFIG_DDR_ECC
131 #ifdef CONFIG_DDR_ECC
132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
133 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
134 #endif
135
136 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
137
138 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
139         !defined(CONFIG_QSPI_BOOT)
140 #define CONFIG_U_QE
141 #endif
142
143 /*
144  * IFC Definitions
145  */
146 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
147 #define CONFIG_FSL_IFC
148 #define CONFIG_SYS_FLASH_BASE           0x60000000
149 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
150
151 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
152 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
153                                 CSPR_PORT_SIZE_16 | \
154                                 CSPR_MSEL_NOR | \
155                                 CSPR_V)
156 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
157 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
158                                 + 0x8000000) | \
159                                 CSPR_PORT_SIZE_16 | \
160                                 CSPR_MSEL_NOR | \
161                                 CSPR_V)
162 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
163
164 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
165                                         CSOR_NOR_TRHZ_80)
166 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
167                                         FTIM0_NOR_TEADC(0x5) | \
168                                         FTIM0_NOR_TEAHC(0x5))
169 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
170                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
171                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
172 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
173                                         FTIM2_NOR_TCH(0x4) | \
174                                         FTIM2_NOR_TWPH(0xe) | \
175                                         FTIM2_NOR_TWP(0x1c))
176 #define CONFIG_SYS_NOR_FTIM3            0
177
178 #define CONFIG_FLASH_CFI_DRIVER
179 #define CONFIG_SYS_FLASH_CFI
180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
181 #define CONFIG_SYS_FLASH_QUIET_TEST
182 #define CONFIG_FLASH_SHOW_PROGRESS      45
183 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
184 #define CONFIG_SYS_WRITE_SWAPPED_DATA
185
186 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
187 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
188 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
190
191 #define CONFIG_SYS_FLASH_EMPTY_INFO
192 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
193                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
194
195 /*
196  * NAND Flash Definitions
197  */
198 #define CONFIG_NAND_FSL_IFC
199
200 #define CONFIG_SYS_NAND_BASE            0x7e800000
201 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
202
203 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
204
205 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
206                                 | CSPR_PORT_SIZE_8      \
207                                 | CSPR_MSEL_NAND        \
208                                 | CSPR_V)
209 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
210 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
211                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
212                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
213                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
214                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
215                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
216                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
217
218 #define CONFIG_SYS_NAND_ONFI_DETECTION
219
220 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
221                                         FTIM0_NAND_TWP(0x18)   | \
222                                         FTIM0_NAND_TWCHT(0x7) | \
223                                         FTIM0_NAND_TWH(0xa))
224 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
225                                         FTIM1_NAND_TWBE(0x39)  | \
226                                         FTIM1_NAND_TRR(0xe)   | \
227                                         FTIM1_NAND_TRP(0x18))
228 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
229                                         FTIM2_NAND_TREH(0xa) | \
230                                         FTIM2_NAND_TWHRE(0x1e))
231 #define CONFIG_SYS_NAND_FTIM3           0x0
232
233 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
234 #define CONFIG_SYS_MAX_NAND_DEVICE      1
235 #define CONFIG_CMD_NAND
236
237 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
238 #endif
239
240 /*
241  * QIXIS Definitions
242  */
243 #define CONFIG_FSL_QIXIS
244
245 #ifdef CONFIG_FSL_QIXIS
246 #define QIXIS_BASE                      0x7fb00000
247 #define QIXIS_BASE_PHYS                 QIXIS_BASE
248 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
249 #define QIXIS_LBMAP_SWITCH              6
250 #define QIXIS_LBMAP_MASK                0x0f
251 #define QIXIS_LBMAP_SHIFT               0
252 #define QIXIS_LBMAP_DFLTBANK            0x00
253 #define QIXIS_LBMAP_ALTBANK             0x04
254 #define QIXIS_PWR_CTL                   0x21
255 #define QIXIS_PWR_CTL_POWEROFF          0x80
256 #define QIXIS_RST_CTL_RESET             0x44
257 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
258 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
259 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
260 #define QIXIS_CTL_SYS                   0x5
261 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
262 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
263 #define QIXIS_RST_FORCE_3               0x45
264 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
265 #define QIXIS_PWR_CTL2                  0x21
266 #define QIXIS_PWR_CTL2_PCTL             0x2
267
268 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
269 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
270                                         CSPR_PORT_SIZE_8 | \
271                                         CSPR_MSEL_GPCM | \
272                                         CSPR_V)
273 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
274 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
275                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
276                                         CSOR_NOR_TRHZ_80)
277
278 /*
279  * QIXIS Timing parameters for IFC GPCM
280  */
281 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
282                                         FTIM0_GPCM_TEADC(0xe) | \
283                                         FTIM0_GPCM_TEAHC(0xe))
284 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
285                                         FTIM1_GPCM_TRAD(0x1f))
286 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
287                                         FTIM2_GPCM_TCH(0xe) | \
288                                         FTIM2_GPCM_TWP(0xf0))
289 #define CONFIG_SYS_FPGA_FTIM3           0x0
290 #endif
291
292 #if defined(CONFIG_NAND_BOOT)
293 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
294 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
295 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
296 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
297 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
298 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
299 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
300 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
301 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
302 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
303 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
304 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
305 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
306 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
307 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
308 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
309 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
310 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
311 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
312 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
313 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
314 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
315 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
316 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
318 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
319 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
320 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
321 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
322 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
323 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
324 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
325 #else
326 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
327 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
328 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
329 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
330 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
331 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
332 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
333 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
334 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
335 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
336 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
337 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
338 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
339 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
340 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
341 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
343 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
344 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
345 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
346 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
347 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
348 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
349 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
350 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
351 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
352 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
353 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
354 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
355 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
356 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
357 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
358 #endif
359
360 /*
361  * Serial Port
362  */
363 #ifdef CONFIG_LPUART
364 #define CONFIG_LPUART_32B_REG
365 #else
366 #define CONFIG_CONS_INDEX               1
367 #define CONFIG_SYS_NS16550_SERIAL
368 #ifndef CONFIG_DM_SERIAL
369 #define CONFIG_SYS_NS16550_REG_SIZE     1
370 #endif
371 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
372 #endif
373
374 #define CONFIG_BAUDRATE                 115200
375
376 /*
377  * I2C
378  */
379 #define CONFIG_SYS_I2C
380 #define CONFIG_SYS_I2C_MXC
381 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
382 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
383 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
384
385 /*
386  * I2C bus multiplexer
387  */
388 #define I2C_MUX_PCA_ADDR_PRI            0x77
389 #define I2C_MUX_CH_DEFAULT              0x8
390 #define I2C_MUX_CH_CH7301               0xC
391
392 /*
393  * MMC
394  */
395 #define CONFIG_FSL_ESDHC
396
397 /* SPI */
398 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
399 /* QSPI */
400 #define QSPI0_AMBA_BASE                 0x40000000
401 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
402 #define FSL_QSPI_FLASH_NUM              2
403
404 /* DSPI */
405
406 /* DM SPI */
407 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
408 #define CONFIG_DM_SPI_FLASH
409 #define CONFIG_SPI_FLASH_DATAFLASH
410 #endif
411 #endif
412
413 /*
414  * USB
415  */
416 /* EHCI Support - disbaled by default */
417 /*#define CONFIG_HAS_FSL_DR_USB*/
418
419 #ifdef CONFIG_HAS_FSL_DR_USB
420 #define CONFIG_USB_EHCI
421 #define CONFIG_USB_EHCI_FSL
422 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
423 #endif
424
425 /*XHCI Support - enabled by default*/
426 #define CONFIG_HAS_FSL_XHCI_USB
427
428 #ifdef CONFIG_HAS_FSL_XHCI_USB
429 #define CONFIG_USB_XHCI_FSL
430 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
431 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
432 #endif
433
434 /*
435  * Video
436  */
437 #define CONFIG_FSL_DCU_FB
438
439 #ifdef CONFIG_FSL_DCU_FB
440 #define CONFIG_CMD_BMP
441 #define CONFIG_VIDEO_LOGO
442 #define CONFIG_VIDEO_BMP_LOGO
443
444 #define CONFIG_FSL_DIU_CH7301
445 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
446 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
447 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
448 #endif
449
450 /*
451  * eTSEC
452  */
453 #define CONFIG_TSEC_ENET
454
455 #ifdef CONFIG_TSEC_ENET
456 #define CONFIG_MII
457 #define CONFIG_MII_DEFAULT_TSEC         3
458 #define CONFIG_TSEC1                    1
459 #define CONFIG_TSEC1_NAME               "eTSEC1"
460 #define CONFIG_TSEC2                    1
461 #define CONFIG_TSEC2_NAME               "eTSEC2"
462 #define CONFIG_TSEC3                    1
463 #define CONFIG_TSEC3_NAME               "eTSEC3"
464
465 #define TSEC1_PHY_ADDR                  1
466 #define TSEC2_PHY_ADDR                  2
467 #define TSEC3_PHY_ADDR                  3
468
469 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
470 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
471 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
472
473 #define TSEC1_PHYIDX                    0
474 #define TSEC2_PHYIDX                    0
475 #define TSEC3_PHYIDX                    0
476
477 #define CONFIG_ETHPRIME                 "eTSEC1"
478
479 #define CONFIG_PHY_GIGE
480 #define CONFIG_PHYLIB
481 #define CONFIG_PHY_REALTEK
482
483 #define CONFIG_HAS_ETH0
484 #define CONFIG_HAS_ETH1
485 #define CONFIG_HAS_ETH2
486
487 #define CONFIG_FSL_SGMII_RISER          1
488 #define SGMII_RISER_PHY_OFFSET          0x1b
489
490 #ifdef CONFIG_FSL_SGMII_RISER
491 #define CONFIG_SYS_TBIPA_VALUE          8
492 #endif
493
494 #endif
495
496 /* PCIe */
497 #define CONFIG_PCIE1            /* PCIE controller 1 */
498 #define CONFIG_PCIE2            /* PCIE controller 2 */
499
500 #ifdef CONFIG_PCI
501 #define CONFIG_PCI_SCAN_SHOW
502 #define CONFIG_CMD_PCI
503 #endif
504
505 #define CONFIG_CMDLINE_TAG
506 #define CONFIG_CMDLINE_EDITING
507
508 #define CONFIG_PEN_ADDR_BIG_ENDIAN
509 #define CONFIG_LAYERSCAPE_NS_ACCESS
510 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
511 #define CONFIG_TIMER_CLK_FREQ           12500000
512
513 #define CONFIG_HWCONFIG
514 #define HWCONFIG_BUFFER_SIZE            256
515
516 #define CONFIG_FSL_DEVICE_DISABLE
517
518
519 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
520
521 #ifdef CONFIG_LPUART
522 #define CONFIG_EXTRA_ENV_SETTINGS       \
523         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
524         "fdt_high=0xffffffff\0"         \
525         "initrd_high=0xffffffff\0"      \
526         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
527 #else
528 #define CONFIG_EXTRA_ENV_SETTINGS       \
529         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
530         "fdt_high=0xffffffff\0"         \
531         "initrd_high=0xffffffff\0"      \
532         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
533 #endif
534
535 /*
536  * Miscellaneous configurable options
537  */
538 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
539 #define CONFIG_AUTO_COMPLETE
540 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
541 #define CONFIG_SYS_PBSIZE               \
542                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
543 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
544 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
545
546 #define CONFIG_SYS_MEMTEST_START        0x80000000
547 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
548
549 #define CONFIG_SYS_LOAD_ADDR            0x82000000
550
551 #define CONFIG_LS102XA_STREAM_ID
552
553 /*
554  * Stack sizes
555  * The stack sizes are set up in start.S using the settings below
556  */
557 #define CONFIG_STACKSIZE                (30 * 1024)
558
559 #define CONFIG_SYS_INIT_SP_OFFSET \
560         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
561 #define CONFIG_SYS_INIT_SP_ADDR \
562         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
563
564 #ifdef CONFIG_SPL_BUILD
565 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
566 #else
567 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
568 #endif
569
570 /*
571  * Environment
572  */
573 #define CONFIG_ENV_OVERWRITE
574
575 #if defined(CONFIG_SD_BOOT)
576 #define CONFIG_ENV_OFFSET               0x100000
577 #define CONFIG_ENV_IS_IN_MMC
578 #define CONFIG_SYS_MMC_ENV_DEV          0
579 #define CONFIG_ENV_SIZE                 0x2000
580 #elif defined(CONFIG_QSPI_BOOT)
581 #define CONFIG_ENV_IS_IN_SPI_FLASH
582 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
583 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
584 #define CONFIG_ENV_SECT_SIZE            0x10000
585 #elif defined(CONFIG_NAND_BOOT)
586 #define CONFIG_ENV_IS_IN_NAND
587 #define CONFIG_ENV_SIZE                 0x2000
588 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
589 #else
590 #define CONFIG_ENV_IS_IN_FLASH
591 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
592 #define CONFIG_ENV_SIZE                 0x2000
593 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
594 #endif
595
596 #define CONFIG_MISC_INIT_R
597
598 /* Hash command with SHA acceleration supported in hardware */
599 #ifdef CONFIG_FSL_CAAM
600 #define CONFIG_CMD_HASH
601 #define CONFIG_SHA_HW_ACCEL
602 #endif
603
604 #include <asm/fsl_secure_boot.h>
605 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
606
607 #endif