include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO
  20
  21 #define CONFIG_BOARD_EARLY_INIT_F
  22
  23 #define CONFIG_DEEP_SLEEP
  24 #if defined(CONFIG_DEEP_SLEEP)
  25 #define CONFIG_SILENT_CONSOLE
  26 #endif
  27
  28 /*
  29  * Size of malloc() pool
  30  */
  31 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  32
  33 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  34 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  35
  36 /*
  37  * Generic Timer Definitions
  38  */
  39 #define GENERIC_TIMER_CLK               12500000
  40
  41 #ifndef __ASSEMBLY__
  42 unsigned long get_board_sys_clk(void);
  43 unsigned long get_board_ddr_clk(void);
  44 #endif
  45
  46 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  47 #define CONFIG_SYS_CLK_FREQ             100000000
  48 #define CONFIG_DDR_CLK_FREQ             100000000
  49 #define CONFIG_QIXIS_I2C_ACCESS
  50 #else
  51 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  52 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  53 #endif
  54
  55 #ifdef CONFIG_RAMBOOT_PBL
  56 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  57 #endif
  58
  59 #ifdef CONFIG_SD_BOOT
  60 #ifdef CONFIG_SD_BOOT_QSPI
  61 #define CONFIG_SYS_FSL_PBL_RCW  \
  62         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  63 #else
  64 #define CONFIG_SYS_FSL_PBL_RCW  \
  65         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  66 #endif
  67 #define CONFIG_SPL_FRAMEWORK
  68 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x600
  71
  72 #define CONFIG_SPL_TEXT_BASE            0x10000000
  73 #define CONFIG_SPL_MAX_SIZE             0x1a000
  74 #define CONFIG_SPL_STACK                0x1001d000
  75 #define CONFIG_SPL_PAD_TO               0x1c000
  76 #define CONFIG_SYS_TEXT_BASE            0x82000000
  77
  78 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  79                 CONFIG_SYS_MONITOR_LEN)
  80 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  81 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  82 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  83 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  84 #endif
  85
  86 #ifdef CONFIG_QSPI_BOOT
  87 #define CONFIG_SYS_TEXT_BASE            0x40010000
  88 #endif
  89
  90 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  91 #define CONFIG_SYS_NO_FLASH
  92 #endif
  93
  94 #ifdef CONFIG_NAND_BOOT
  95 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  96 #define CONFIG_SPL_FRAMEWORK
  97 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  98
  99 #define CONFIG_SPL_TEXT_BASE            0x10000000
 100 #define CONFIG_SPL_MAX_SIZE             0x1a000
 101 #define CONFIG_SPL_STACK                0x1001d000
 102 #define CONFIG_SPL_PAD_TO               0x1c000
 103 #define CONFIG_SYS_TEXT_BASE            0x82000000
 104
 105 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 107 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 108 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 109 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 110
 111 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 112 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 113 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 114 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 115 #define CONFIG_SYS_MONITOR_LEN          0x80000
 116 #endif
 117
 118 #ifndef CONFIG_SYS_TEXT_BASE
 119 #define CONFIG_SYS_TEXT_BASE            0x60100000
 120 #endif
 121
 122 #define CONFIG_NR_DRAM_BANKS            1
 123
 124 #define CONFIG_DDR_SPD
 125 #define SPD_EEPROM_ADDRESS              0x51
 126 #define CONFIG_SYS_SPD_BUS_NUM          0
 127
 128 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
 129 #ifndef CONFIG_SYS_FSL_DDR4
 130 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
 131 #define CONFIG_SYS_DDR_RAW_TIMING
 132 #endif
 133 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 134 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 135
 136 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 137 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 138
 139 #define CONFIG_DDR_ECC
 140 #ifdef CONFIG_DDR_ECC
 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 142 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 143 #endif
 144
 145 #define CONFIG_SYS_HAS_SERDES
 146
 147 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 148
 149 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 150         !defined(CONFIG_QSPI_BOOT)
 151 #define CONFIG_U_QE
 152 #endif
 153
 154 /*
 155  * IFC Definitions
 156  */
 157 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 158 #define CONFIG_FSL_IFC
 159 #define CONFIG_SYS_FLASH_BASE           0x60000000
 160 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 161
 162 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 163 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 164                                 CSPR_PORT_SIZE_16 | \
 165                                 CSPR_MSEL_NOR | \
 166                                 CSPR_V)
 167 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 168 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 169                                 + 0x8000000) | \
 170                                 CSPR_PORT_SIZE_16 | \
 171                                 CSPR_MSEL_NOR | \
 172                                 CSPR_V)
 173 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 174
 175 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 176                                         CSOR_NOR_TRHZ_80)
 177 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 178                                         FTIM0_NOR_TEADC(0x5) | \
 179                                         FTIM0_NOR_TEAHC(0x5))
 180 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 181                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 182                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 183 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 184                                         FTIM2_NOR_TCH(0x4) | \
 185                                         FTIM2_NOR_TWPH(0xe) | \
 186                                         FTIM2_NOR_TWP(0x1c))
 187 #define CONFIG_SYS_NOR_FTIM3            0
 188
 189 #define CONFIG_FLASH_CFI_DRIVER
 190 #define CONFIG_SYS_FLASH_CFI
 191 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 192 #define CONFIG_SYS_FLASH_QUIET_TEST
 193 #define CONFIG_FLASH_SHOW_PROGRESS      45
 194 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 195 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 196
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 199 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 200 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 201
 202 #define CONFIG_SYS_FLASH_EMPTY_INFO
 203 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 204                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 205
 206 /*
 207  * NAND Flash Definitions
 208  */
 209 #define CONFIG_NAND_FSL_IFC
 210
 211 #define CONFIG_SYS_NAND_BASE            0x7e800000
 212 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 213
 214 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 215
 216 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 217                                 | CSPR_PORT_SIZE_8      \
 218                                 | CSPR_MSEL_NAND        \
 219                                 | CSPR_V)
 220 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 221 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 222                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 223                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 224                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 225                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 226                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 227                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 228
 229 #define CONFIG_SYS_NAND_ONFI_DETECTION
 230
 231 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 232                                         FTIM0_NAND_TWP(0x18)   | \
 233                                         FTIM0_NAND_TWCHT(0x7) | \
 234                                         FTIM0_NAND_TWH(0xa))
 235 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 236                                         FTIM1_NAND_TWBE(0x39)  | \
 237                                         FTIM1_NAND_TRR(0xe)   | \
 238                                         FTIM1_NAND_TRP(0x18))
 239 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 240                                         FTIM2_NAND_TREH(0xa) | \
 241                                         FTIM2_NAND_TWHRE(0x1e))
 242 #define CONFIG_SYS_NAND_FTIM3           0x0
 243
 244 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 245 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 246 #define CONFIG_CMD_NAND
 247
 248 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 249 #endif
 250
 251 /*
 252  * QIXIS Definitions
 253  */
 254 #define CONFIG_FSL_QIXIS
 255
 256 #ifdef CONFIG_FSL_QIXIS
 257 #define QIXIS_BASE                      0x7fb00000
 258 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 259 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 260 #define QIXIS_LBMAP_SWITCH              6
 261 #define QIXIS_LBMAP_MASK                0x0f
 262 #define QIXIS_LBMAP_SHIFT               0
 263 #define QIXIS_LBMAP_DFLTBANK            0x00
 264 #define QIXIS_LBMAP_ALTBANK             0x04
 265 #define QIXIS_PWR_CTL                   0x21
 266 #define QIXIS_PWR_CTL_POWEROFF          0x80
 267 #define QIXIS_RST_CTL_RESET             0x44
 268 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 269 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 270 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 271 #define QIXIS_CTL_SYS                   0x5
 272 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 273 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 274 #define QIXIS_RST_FORCE_3               0x45
 275 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 276 #define QIXIS_PWR_CTL2                  0x21
 277 #define QIXIS_PWR_CTL2_PCTL             0x2
 278
 279 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 280 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 281                                         CSPR_PORT_SIZE_8 | \
 282                                         CSPR_MSEL_GPCM | \
 283                                         CSPR_V)
 284 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 285 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 286                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 287                                         CSOR_NOR_TRHZ_80)
 288
 289 /*
 290  * QIXIS Timing parameters for IFC GPCM
 291  */
 292 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 293                                         FTIM0_GPCM_TEADC(0xe) | \
 294                                         FTIM0_GPCM_TEAHC(0xe))
 295 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 296                                         FTIM1_GPCM_TRAD(0x1f))
 297 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 298                                         FTIM2_GPCM_TCH(0xe) | \
 299                                         FTIM2_GPCM_TWP(0xf0))
 300 #define CONFIG_SYS_FPGA_FTIM3           0x0
 301 #endif
 302
 303 #if defined(CONFIG_NAND_BOOT)
 304 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 305 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 306 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 307 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 308 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 309 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 310 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 311 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 312 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 313 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 314 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 315 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 316 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 317 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 318 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 319 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 320 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 321 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 322 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 323 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 324 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 325 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 326 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 327 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 328 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 329 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 330 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 331 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 332 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 333 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 334 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 335 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 336 #else
 337 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 338 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 339 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 340 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 341 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 342 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 343 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 344 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 345 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 346 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 347 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 348 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 349 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 350 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 351 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 352 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 353 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 354 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 355 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 356 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 357 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 358 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 359 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 360 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 361 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 362 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 363 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 364 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 365 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 366 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 367 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 368 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 369 #endif
 370
 371 /*
 372  * Serial Port
 373  */
 374 #ifdef CONFIG_LPUART
 375 #define CONFIG_LPUART_32B_REG
 376 #else
 377 #define CONFIG_CONS_INDEX               1
 378 #define CONFIG_SYS_NS16550_SERIAL
 379 #ifndef CONFIG_DM_SERIAL
 380 #define CONFIG_SYS_NS16550_REG_SIZE     1
 381 #endif
 382 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 383 #endif
 384
 385 #define CONFIG_BAUDRATE                 115200
 386
 387 /*
 388  * I2C
 389  */
 390 #define CONFIG_SYS_I2C
 391 #define CONFIG_SYS_I2C_MXC
 392 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 393 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 394 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 395
 396 /*
 397  * I2C bus multiplexer
 398  */
 399 #define I2C_MUX_PCA_ADDR_PRI            0x77
 400 #define I2C_MUX_CH_DEFAULT              0x8
 401 #define I2C_MUX_CH_CH7301               0xC
 402
 403 /*
 404  * MMC
 405  */
 406 #define CONFIG_MMC
 407 #define CONFIG_FSL_ESDHC
 408 #define CONFIG_GENERIC_MMC
 409
 410 #define CONFIG_DOS_PARTITION
 411
 412 /* SPI */
 413 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 414 /* QSPI */
 415 #define QSPI0_AMBA_BASE                 0x40000000
 416 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 417 #define FSL_QSPI_FLASH_NUM              2
 418
 419 /* DSPI */
 420
 421 /* DM SPI */
 422 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 423 #define CONFIG_DM_SPI_FLASH
 424 #define CONFIG_SPI_FLASH_DATAFLASH
 425 #endif
 426 #endif
 427
 428 /*
 429  * USB
 430  */
 431 /* EHCI Support - disbaled by default */
 432 /*#define CONFIG_HAS_FSL_DR_USB*/
 433
 434 #ifdef CONFIG_HAS_FSL_DR_USB
 435 #define CONFIG_USB_EHCI
 436 #define CONFIG_USB_EHCI_FSL
 437 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 438 #endif
 439
 440 /*XHCI Support - enabled by default*/
 441 #define CONFIG_HAS_FSL_XHCI_USB
 442
 443 #ifdef CONFIG_HAS_FSL_XHCI_USB
 444 #define CONFIG_USB_XHCI_FSL
 445 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 446 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 447 #endif
 448
 449 /*
 450  * Video
 451  */
 452 #define CONFIG_FSL_DCU_FB
 453
 454 #ifdef CONFIG_FSL_DCU_FB
 455 #define CONFIG_VIDEO
 456 #define CONFIG_CMD_BMP
 457 #define CONFIG_CFB_CONSOLE
 458 #define CONFIG_VGA_AS_SINGLE_DEVICE
 459 #define CONFIG_VIDEO_LOGO
 460 #define CONFIG_VIDEO_BMP_LOGO
 461 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 462
 463 #define CONFIG_FSL_DIU_CH7301
 464 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 465 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 466 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 467 #endif
 468
 469 /*
 470  * eTSEC
 471  */
 472 #define CONFIG_TSEC_ENET
 473
 474 #ifdef CONFIG_TSEC_ENET
 475 #define CONFIG_MII
 476 #define CONFIG_MII_DEFAULT_TSEC         3
 477 #define CONFIG_TSEC1                    1
 478 #define CONFIG_TSEC1_NAME               "eTSEC1"
 479 #define CONFIG_TSEC2                    1
 480 #define CONFIG_TSEC2_NAME               "eTSEC2"
 481 #define CONFIG_TSEC3                    1
 482 #define CONFIG_TSEC3_NAME               "eTSEC3"
 483
 484 #define TSEC1_PHY_ADDR                  1
 485 #define TSEC2_PHY_ADDR                  2
 486 #define TSEC3_PHY_ADDR                  3
 487
 488 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 489 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 490 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 491
 492 #define TSEC1_PHYIDX                    0
 493 #define TSEC2_PHYIDX                    0
 494 #define TSEC3_PHYIDX                    0
 495
 496 #define CONFIG_ETHPRIME                 "eTSEC1"
 497
 498 #define CONFIG_PHY_GIGE
 499 #define CONFIG_PHYLIB
 500 #define CONFIG_PHY_REALTEK
 501
 502 #define CONFIG_HAS_ETH0
 503 #define CONFIG_HAS_ETH1
 504 #define CONFIG_HAS_ETH2
 505
 506 #define CONFIG_FSL_SGMII_RISER          1
 507 #define SGMII_RISER_PHY_OFFSET          0x1b
 508
 509 #ifdef CONFIG_FSL_SGMII_RISER
 510 #define CONFIG_SYS_TBIPA_VALUE          8
 511 #endif
 512
 513 #endif
 514
 515 /* PCIe */
 516 #define CONFIG_PCI              /* Enable PCI/PCIE */
 517 #define CONFIG_PCIE1            /* PCIE controller 1 */
 518 #define CONFIG_PCIE2            /* PCIE controller 2 */
 519 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 520 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 521
 522 #define CONFIG_SYS_PCI_64BIT
 523
 524 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 525 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 526 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 527 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 528
 529 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 530 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 531 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 532
 533 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 534 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 535 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 536
 537 #ifdef CONFIG_PCI
 538 #define CONFIG_PCI_PNP
 539 #define CONFIG_PCI_SCAN_SHOW
 540 #define CONFIG_CMD_PCI
 541 #endif
 542
 543 #define CONFIG_CMDLINE_TAG
 544 #define CONFIG_CMDLINE_EDITING
 545
 546 #define CONFIG_ARMV7_NONSEC
 547 #define CONFIG_ARMV7_VIRT
 548 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 549 #define CONFIG_LAYERSCAPE_NS_ACCESS
 550 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 551 #define CONFIG_TIMER_CLK_FREQ           12500000
 552
 553 #define CONFIG_HWCONFIG
 554 #define HWCONFIG_BUFFER_SIZE            256
 555
 556 #define CONFIG_FSL_DEVICE_DISABLE
 557
 558
 559 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 560
 561 #ifdef CONFIG_LPUART
 562 #define CONFIG_EXTRA_ENV_SETTINGS       \
 563         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 564         "fdt_high=0xffffffff\0"         \
 565         "initrd_high=0xffffffff\0"      \
 566         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 567 #else
 568 #define CONFIG_EXTRA_ENV_SETTINGS       \
 569         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 570         "fdt_high=0xffffffff\0"         \
 571         "initrd_high=0xffffffff\0"      \
 572         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 573 #endif
 574
 575 /*
 576  * Miscellaneous configurable options
 577  */
 578 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 579 #define CONFIG_AUTO_COMPLETE
 580 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 581 #define CONFIG_SYS_PBSIZE               \
 582                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 583 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 584 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 585
 586 #define CONFIG_SYS_MEMTEST_START        0x80000000
 587 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 588
 589 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 590
 591 #define CONFIG_LS102XA_STREAM_ID
 592
 593 /*
 594  * Stack sizes
 595  * The stack sizes are set up in start.S using the settings below
 596  */
 597 #define CONFIG_STACKSIZE                (30 * 1024)
 598
 599 #define CONFIG_SYS_INIT_SP_OFFSET \
 600         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 601 #define CONFIG_SYS_INIT_SP_ADDR \
 602         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 603
 604 #ifdef CONFIG_SPL_BUILD
 605 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 606 #else
 607 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 608 #endif
 609
 610 /*
 611  * Environment
 612  */
 613 #define CONFIG_ENV_OVERWRITE
 614
 615 #if defined(CONFIG_SD_BOOT)
 616 #define CONFIG_ENV_OFFSET               0x100000
 617 #define CONFIG_ENV_IS_IN_MMC
 618 #define CONFIG_SYS_MMC_ENV_DEV          0
 619 #define CONFIG_ENV_SIZE                 0x2000
 620 #elif defined(CONFIG_QSPI_BOOT)
 621 #define CONFIG_ENV_IS_IN_SPI_FLASH
 622 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 623 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 624 #define CONFIG_ENV_SECT_SIZE            0x10000
 625 #elif defined(CONFIG_NAND_BOOT)
 626 #define CONFIG_ENV_IS_IN_NAND
 627 #define CONFIG_ENV_SIZE                 0x2000
 628 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 629 #else
 630 #define CONFIG_ENV_IS_IN_FLASH
 631 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 632 #define CONFIG_ENV_SIZE                 0x2000
 633 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 634 #endif
 635
 636 #define CONFIG_MISC_INIT_R
 637
 638 /* Hash command with SHA acceleration supported in hardware */
 639 #ifdef CONFIG_FSL_CAAM
 640 #define CONFIG_CMD_HASH
 641 #define CONFIG_SHA_HW_ACCEL
 642 #endif
 643
 644 #include <asm/fsl_secure_boot.h>
 645 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 646
 647 #endif