include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 #define CONFIG_SYS_CLK_FREQ             100000000
  16
  17 /*
  18  * DDR: 800 MHz ( 1600 MT/s data rate )
  19  */
  20
  21 #define DDR_SDRAM_CFG                   0x470c0008
  22 #define DDR_CS0_BNDS                    0x008000bf
  23 #define DDR_CS0_CONFIG                  0x80014302
  24 #define DDR_TIMING_CFG_0                0x50550004
  25 #define DDR_TIMING_CFG_1                0xbcb38c56
  26 #define DDR_TIMING_CFG_2                0x0040d120
  27 #define DDR_TIMING_CFG_3                0x010e1000
  28 #define DDR_TIMING_CFG_4                0x00000001
  29 #define DDR_TIMING_CFG_5                0x03401400
  30 #define DDR_SDRAM_CFG_2                 0x00401010
  31 #define DDR_SDRAM_MODE                  0x00061c60
  32 #define DDR_SDRAM_MODE_2                0x00180000
  33 #define DDR_SDRAM_INTERVAL              0x18600618
  34 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  35 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  36 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  37 #define DDR_DDR_CDR1                    0x80040000
  38 #define DDR_DDR_CDR2                    0x00000001
  39 #define DDR_SDRAM_CLK_CNTL              0x02000000
  40 #define DDR_DDR_ZQ_CNTL                 0x89080600
  41 #define DDR_CS0_CONFIG_2                0
  42 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  43 #define SDRAM_CFG2_D_INIT               0x00000010
  44 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  45 #define SDRAM_CFG2_FRC_SR               0x80000000
  46 #define SDRAM_CFG_BI                    0x00000001
  47
  48 #ifdef CONFIG_SD_BOOT
  49 #define CONFIG_SPL_MAX_SIZE             0x1a000
  50 #define CONFIG_SPL_STACK                0x1001d000
  51 #define CONFIG_SPL_PAD_TO               0x1c000
  52
  53 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  54                 CONFIG_SYS_MONITOR_LEN)
  55 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  56 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  57 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  58 #define CONFIG_SYS_MONITOR_LEN          0x80000
  59 #endif
  60
  61 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  63
  64 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  65
  66 /*
  67  * Serial Port
  68  */
  69 #define CONFIG_SYS_NS16550_SERIAL
  70 #define CONFIG_SYS_NS16550_REG_SIZE     1
  71 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  72
  73 /*
  74  * I2C
  75  */
  76
  77 /* EEPROM */
  78 #define CONFIG_SYS_I2C_EEPROM_NXID
  79 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  80
  81 /*
  82  * MMC
  83  */
  84
  85 /* SATA */
  86 #define CONFIG_SCSI_AHCI_PLAT
  87 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  88 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  89 #endif
  90 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  91         PCI_DEVICE_ID_FREESCALE_AHCI}
  92
  93 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
  94 #define CONFIG_SYS_SCSI_MAX_LUN         1
  95 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  96                 CONFIG_SYS_SCSI_MAX_LUN)
  97
  98 /* SPI */
  99
 100 /*
 101  * eTSEC
 102  */
 103
 104 #ifdef CONFIG_TSEC_ENET
 105 #define CONFIG_MII_DEFAULT_TSEC         1
 106 #define CONFIG_TSEC1                    1
 107 #define CONFIG_TSEC1_NAME               "eTSEC1"
 108 #define CONFIG_TSEC2                    1
 109 #define CONFIG_TSEC2_NAME               "eTSEC2"
 110
 111 #define TSEC1_PHY_ADDR                  1
 112 #define TSEC2_PHY_ADDR                  3
 113
 114 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 115 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 116
 117 #define TSEC1_PHYIDX                    0
 118 #define TSEC2_PHYIDX                    0
 119
 120 #define CONFIG_ETHPRIME                 "eTSEC2"
 121
 122 #define CONFIG_HAS_ETH0
 123 #define CONFIG_HAS_ETH1
 124 #define CONFIG_HAS_ETH2
 125 #endif
 126
 127 /* PCIe */
 128 #define CONFIG_PCIE1            /* PCIE controler 1 */
 129 #define CONFIG_PCIE2            /* PCIE controler 2 */
 130
 131 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 132
 133 #ifdef CONFIG_PCI
 134 #define CONFIG_PCI_SCAN_SHOW
 135 #endif
 136
 137 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 138 #define CONFIG_LAYERSCAPE_NS_ACCESS
 139 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 140 #define COUNTER_FREQUENCY               12500000
 141
 142 #define CONFIG_HWCONFIG
 143 #define HWCONFIG_BUFFER_SIZE            256
 144
 145 #define CONFIG_FSL_DEVICE_DISABLE
 146
 147 #define CONFIG_EXTRA_ENV_SETTINGS       \
 148         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 149 "initrd_high=0xffffffff\0"
 150
 151 /*
 152  * Miscellaneous configurable options
 153  */
 154 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 155
 156 #define CONFIG_LS102XA_STREAM_ID
 157
 158 #define CONFIG_SYS_INIT_SP_OFFSET \
 159         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 160 #define CONFIG_SYS_INIT_SP_ADDR \
 161         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 162
 163 #ifdef CONFIG_SPL_BUILD
 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 165 #else
 166 /* start of monitor */
 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 168 #endif
 169
 170 #include <asm/fsl_secure_boot.h>
 171
 172 #endif