include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  13 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  14
  15 /*
  16  * DDR: 800 MHz ( 1600 MT/s data rate )
  17  */
  18
  19 #define DDR_SDRAM_CFG                   0x470c0008
  20 #define DDR_CS0_BNDS                    0x008000bf
  21 #define DDR_CS0_CONFIG                  0x80014302
  22 #define DDR_TIMING_CFG_0                0x50550004
  23 #define DDR_TIMING_CFG_1                0xbcb38c56
  24 #define DDR_TIMING_CFG_2                0x0040d120
  25 #define DDR_TIMING_CFG_3                0x010e1000
  26 #define DDR_TIMING_CFG_4                0x00000001
  27 #define DDR_TIMING_CFG_5                0x03401400
  28 #define DDR_SDRAM_CFG_2                 0x00401010
  29 #define DDR_SDRAM_MODE                  0x00061c60
  30 #define DDR_SDRAM_MODE_2                0x00180000
  31 #define DDR_SDRAM_INTERVAL              0x18600618
  32 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  33 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  34 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  35 #define DDR_DDR_CDR1                    0x80040000
  36 #define DDR_DDR_CDR2                    0x00000001
  37 #define DDR_SDRAM_CLK_CNTL              0x02000000
  38 #define DDR_DDR_ZQ_CNTL                 0x89080600
  39 #define DDR_CS0_CONFIG_2                0
  40 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  41 #define SDRAM_CFG2_D_INIT               0x00000010
  42 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  43 #define SDRAM_CFG2_FRC_SR               0x80000000
  44 #define SDRAM_CFG_BI                    0x00000001
  45
  46 #ifdef CONFIG_SD_BOOT
  47 #define CONFIG_SPL_MAX_SIZE             0x1a000
  48 #define CONFIG_SPL_STACK                0x1001d000
  49 #define CONFIG_SPL_PAD_TO               0x1c000
  50
  51 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  52                 CONFIG_SYS_MONITOR_LEN)
  53 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  54 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  55 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  56 #define CONFIG_SYS_MONITOR_LEN          0x80000
  57 #endif
  58
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  61
  62 /*
  63  * Serial Port
  64  */
  65 #define CONFIG_SYS_NS16550_SERIAL
  66 #define CONFIG_SYS_NS16550_REG_SIZE     1
  67 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  68
  69 /*
  70  * I2C
  71  */
  72
  73 /* EEPROM */
  74 #define CONFIG_SYS_I2C_EEPROM_NXID
  75 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  76
  77 /*
  78  * MMC
  79  */
  80
  81 /* SATA */
  82 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  83 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  84 #endif
  85 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  86         PCI_DEVICE_ID_FREESCALE_AHCI}
  87
  88 /* SPI */
  89
  90 /*
  91  * eTSEC
  92  */
  93
  94 #ifdef CONFIG_TSEC_ENET
  95 #define CONFIG_MII_DEFAULT_TSEC         1
  96 #define CONFIG_TSEC1                    1
  97 #define CONFIG_TSEC1_NAME               "eTSEC1"
  98 #define CONFIG_TSEC2                    1
  99 #define CONFIG_TSEC2_NAME               "eTSEC2"
 100
 101 #define TSEC1_PHY_ADDR                  1
 102 #define TSEC2_PHY_ADDR                  3
 103
 104 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 105 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 106
 107 #define TSEC1_PHYIDX                    0
 108 #define TSEC2_PHYIDX                    0
 109
 110 #define CONFIG_ETHPRIME                 "eTSEC2"
 111
 112 #define CONFIG_HAS_ETH0
 113 #define CONFIG_HAS_ETH1
 114 #define CONFIG_HAS_ETH2
 115 #endif
 116
 117 /* PCIe */
 118 #define CONFIG_PCIE1            /* PCIE controler 1 */
 119 #define CONFIG_PCIE2            /* PCIE controler 2 */
 120
 121 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 122
 123 #ifdef CONFIG_PCI
 124 #define CONFIG_PCI_SCAN_SHOW
 125 #endif
 126
 127 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 128 #define CONFIG_LAYERSCAPE_NS_ACCESS
 129 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 130 #define COUNTER_FREQUENCY               12500000
 131
 132 #define CONFIG_HWCONFIG
 133 #define HWCONFIG_BUFFER_SIZE            256
 134
 135 #define CONFIG_FSL_DEVICE_DISABLE
 136
 137 #define CONFIG_EXTRA_ENV_SETTINGS       \
 138         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 139 "initrd_high=0xffffffff\0"
 140
 141 /*
 142  * Miscellaneous configurable options
 143  */
 144 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 145
 146 #define CONFIG_LS102XA_STREAM_ID
 147
 148 #define CONFIG_SYS_INIT_SP_OFFSET \
 149         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 150 #define CONFIG_SYS_INIT_SP_ADDR \
 151         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 152
 153 #ifdef CONFIG_SPL_BUILD
 154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 155 #else
 156 /* start of monitor */
 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 158 #endif
 159
 160 #include <asm/fsl_secure_boot.h>
 161
 162 #endif