include/configs/ls1021aiot.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 /*
  15  * Size of malloc() pool
  16  */
  17 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  18
  19 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  20 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  21
  22 /* XHCI Support - enabled by default */
  23 #define CONFIG_HAS_FSL_XHCI_USB
  24
  25 #ifdef CONFIG_HAS_FSL_XHCI_USB
  26 #define CONFIG_USB_XHCI_FSL
  27 #define CONFIG_USB_XHCI_DWC3
  28 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
  29 #endif
  30
  31 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
  32 #define CONFIG_USB_STORAGE
  33 #define CONFIG_CMD_EXT2
  34 #endif
  35
  36 #define CONFIG_SYS_CLK_FREQ             100000000
  37 #define CONFIG_DDR_CLK_FREQ             100000000
  38
  39 /*
  40  * DDR: 800 MHz ( 1600 MT/s data rate )
  41  */
  42
  43 #define DDR_SDRAM_CFG                   0x470c0008
  44 #define DDR_CS0_BNDS                    0x008000bf
  45 #define DDR_CS0_CONFIG                  0x80014302
  46 #define DDR_TIMING_CFG_0                0x50550004
  47 #define DDR_TIMING_CFG_1                0xbcb38c56
  48 #define DDR_TIMING_CFG_2                0x0040d120
  49 #define DDR_TIMING_CFG_3                0x010e1000
  50 #define DDR_TIMING_CFG_4                0x00000001
  51 #define DDR_TIMING_CFG_5                0x03401400
  52 #define DDR_SDRAM_CFG_2                 0x00401010
  53 #define DDR_SDRAM_MODE                  0x00061c60
  54 #define DDR_SDRAM_MODE_2                0x00180000
  55 #define DDR_SDRAM_INTERVAL              0x18600618
  56 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  57 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  58 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  59 #define DDR_DDR_CDR1                    0x80040000
  60 #define DDR_DDR_CDR2                    0x00000001
  61 #define DDR_SDRAM_CLK_CNTL              0x02000000
  62 #define DDR_DDR_ZQ_CNTL                 0x89080600
  63 #define DDR_CS0_CONFIG_2                0
  64 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  65 #define SDRAM_CFG2_D_INIT               0x00000010
  66 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  67 #define SDRAM_CFG2_FRC_SR               0x80000000
  68 #define SDRAM_CFG_BI                    0x00000001
  69
  70 #ifdef CONFIG_RAMBOOT_PBL
  71 #define CONFIG_SYS_FSL_PBL_PBI  \
  72         board/freescale/ls1021aiot/ls102xa_pbi.cfg
  73 #endif
  74
  75 #ifdef CONFIG_SD_BOOT
  76 #define CONFIG_SYS_FSL_PBL_RCW  \
  77         board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
  78 #define CONFIG_SPL_FRAMEWORK
  79 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  80 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  81 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  82 #define CONFIG_SPL_ENV_SUPPORT
  83 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  84 #define CONFIG_SPL_I2C_SUPPORT
  85 #define CONFIG_SPL_WATCHDOG_SUPPORT
  86 #define CONFIG_SPL_SERIAL_SUPPORT
  87 #define CONFIG_SPL_MMC_SUPPORT
  88 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  89
  90 #define CONFIG_SPL_TEXT_BASE    0x10000000
  91 #define CONFIG_SPL_MAX_SIZE             0x1a000
  92 #define CONFIG_SPL_STACK                0x1001d000
  93 #define CONFIG_SPL_PAD_TO               0x1c000
  94 #define CONFIG_SYS_TEXT_BASE    0x82000000
  95
  96 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  97                 CONFIG_SYS_MONITOR_LEN)
  98 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  99 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 100 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 101 #define CONFIG_SYS_MONITOR_LEN          0x80000
 102 #endif
 103
 104 #ifdef CONFIG_QSPI_BOOT
 105 #define CONFIG_SYS_TEXT_BASE            0x40010000
 106 #endif
 107
 108 #define CONFIG_NR_DRAM_BANKS            1
 109
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112
 113 /*
 114  * Serial Port
 115  */
 116 #define CONFIG_CONS_INDEX               1
 117 #define CONFIG_SYS_NS16550_SERIAL
 118 #define CONFIG_SYS_NS16550_REG_SIZE     1
 119 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 120
 121 /*
 122  * I2C
 123  */
 124 #define CONFIG_CMD_I2C
 125 #define CONFIG_SYS_I2C
 126 #define CONFIG_SYS_I2C_MXC
 127 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 128 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 129 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 130
 131 /* EEPROM */
 132 #define CONFIG_ID_EEPROM
 133 #define CONFIG_SYS_I2C_EEPROM_NXID
 134 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 135 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51
 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 137
 138 /*
 139  * MMC
 140  */
 141 #define CONFIG_CMD_MMC
 142 #define CONFIG_FSL_ESDHC
 143
 144 /* SATA */
 145 #define CONFIG_LIBATA
 146 #define CONFIG_SCSI_AHCI
 147 #define CONFIG_SCSI_AHCI_PLAT
 148 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
 149 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
 150 #endif
 151 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
 152         PCI_DEVICE_ID_FREESCALE_AHCI}
 153
 154 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 155 #define CONFIG_SYS_SCSI_MAX_LUN         1
 156 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 157                 CONFIG_SYS_SCSI_MAX_LUN)
 158
 159 /* SPI */
 160 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 161 #define CONFIG_SPI_FLASH_SPANSION
 162
 163 /* QSPI */
 164 #define QSPI0_AMBA_BASE                 0x40000000
 165 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 166 #define FSL_QSPI_FLASH_NUM              2
 167 #define CONFIG_SPI_FLASH_BAR
 168 #define CONFIG_SPI_FLASH_SPANSION
 169 #endif
 170
 171 /* DM SPI */
 172 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 173 #define CONFIG_CMD_SF
 174 #define CONFIG_DM_SPI_FLASH
 175 #endif
 176
 177 /*
 178  * eTSEC
 179  */
 180 #define CONFIG_TSEC_ENET
 181
 182 #ifdef CONFIG_TSEC_ENET
 183 #define CONFIG_MII
 184 #define CONFIG_MII_DEFAULT_TSEC         1
 185 #define CONFIG_TSEC1                    1
 186 #define CONFIG_TSEC1_NAME               "eTSEC1"
 187 #define CONFIG_TSEC2                    1
 188 #define CONFIG_TSEC2_NAME               "eTSEC2"
 189
 190 #define TSEC1_PHY_ADDR                  1
 191 #define TSEC2_PHY_ADDR                  3
 192
 193 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 194 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 195
 196 #define TSEC1_PHYIDX                    0
 197 #define TSEC2_PHYIDX                    0
 198
 199 #define CONFIG_ETHPRIME                 "eTSEC2"
 200
 201 #define CONFIG_PHY_ATHEROS
 202
 203 #define CONFIG_HAS_ETH0
 204 #define CONFIG_HAS_ETH1
 205 #define CONFIG_HAS_ETH2
 206 #endif
 207
 208 /* PCIe */
 209 #define CONFIG_PCIE1            /* PCIE controler 1 */
 210 #define CONFIG_PCIE2            /* PCIE controler 2 */
 211
 212 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 213
 214 #ifdef CONFIG_PCI
 215 #define CONFIG_PCI_SCAN_SHOW
 216 #endif
 217
 218 #define CONFIG_CMD_PING
 219 #define CONFIG_CMD_DHCP
 220 #define CONFIG_CMD_MII
 221
 222 #define CONFIG_CMDLINE_TAG
 223 #define CONFIG_CMDLINE_EDITING
 224
 225 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT)
 226 #undef  CONFIG_CMD_IMLS
 227 #endif
 228
 229 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 230 #define CONFIG_LAYERSCAPE_NS_ACCESS
 231 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 232 #define COUNTER_FREQUENCY               12500000
 233
 234 #define CONFIG_HWCONFIG
 235 #define HWCONFIG_BUFFER_SIZE            256
 236
 237 #define CONFIG_FSL_DEVICE_DISABLE
 238
 239 #define CONFIG_EXTRA_ENV_SETTINGS       \
 240         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 241 "initrd_high=0xffffffff\0"      \
 242 "fdt_high=0xffffffff\0"
 243
 244 /*
 245  * Miscellaneous configurable options
 246  */
 247 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 248 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 249 #define CONFIG_AUTO_COMPLETE
 250 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 251 #define CONFIG_SYS_PBSIZE               \
 252         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 253 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 254 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 255
 256 #define CONFIG_CMD_GREPENV
 257 #define CONFIG_CMD_MEMINFO
 258
 259 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 260
 261 #define CONFIG_LS102XA_STREAM_ID
 262
 263 #define CONFIG_SYS_INIT_SP_OFFSET \
 264         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 265 #define CONFIG_SYS_INIT_SP_ADDR \
 266         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 267
 268 #ifdef CONFIG_SPL_BUILD
 269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 270 #else
 271 /* start of monitor */
 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 273 #endif
 274
 275 #define CONFIG_SYS_QE_FW_ADDR   0x67f40000
 276
 277 /*
 278  * Environment
 279  */
 280
 281 #define CONFIG_ENV_OVERWRITE
 282
 283 #if defined(CONFIG_SD_BOOT)
 284 #define CONFIG_ENV_OFFSET               0x100000
 285 #define CONFIG_SYS_MMC_ENV_DEV  0
 286 #define CONFIG_ENV_SIZE                 0x2000
 287 #elif defined(CONFIG_QSPI_BOOT)
 288 #define CONFIG_ENV_SIZE                 0x2000
 289 #define CONFIG_ENV_OFFSET               0x100000
 290 #define CONFIG_ENV_SECT_SIZE    0x10000
 291 #endif
 292
 293 #define CONFIG_OF_BOARD_SETUP
 294 #define CONFIG_OF_STDOUT_VIA_ALIAS
 295 #define CONFIG_CMD_BOOTZ
 296
 297 #define CONFIG_MISC_INIT_R
 298
 299 #include <asm/fsl_secure_boot.h>
 300
 301 #endif