include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 /*
  14  * DDR: 800 MHz ( 1600 MT/s data rate )
  15  */
  16
  17 #define DDR_SDRAM_CFG                   0x470c0008
  18 #define DDR_CS0_BNDS                    0x008000bf
  19 #define DDR_CS0_CONFIG                  0x80014302
  20 #define DDR_TIMING_CFG_0                0x50550004
  21 #define DDR_TIMING_CFG_1                0xbcb38c56
  22 #define DDR_TIMING_CFG_2                0x0040d120
  23 #define DDR_TIMING_CFG_3                0x010e1000
  24 #define DDR_TIMING_CFG_4                0x00000001
  25 #define DDR_TIMING_CFG_5                0x03401400
  26 #define DDR_SDRAM_CFG_2                 0x00401010
  27 #define DDR_SDRAM_MODE                  0x00061c60
  28 #define DDR_SDRAM_MODE_2                0x00180000
  29 #define DDR_SDRAM_INTERVAL              0x18600618
  30 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  31 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  32 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  33 #define DDR_DDR_CDR1                    0x80040000
  34 #define DDR_DDR_CDR2                    0x00000001
  35 #define DDR_SDRAM_CLK_CNTL              0x02000000
  36 #define DDR_DDR_ZQ_CNTL                 0x89080600
  37 #define DDR_CS0_CONFIG_2                0
  38 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  39 #define SDRAM_CFG2_D_INIT               0x00000010
  40 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  41 #define SDRAM_CFG2_FRC_SR               0x80000000
  42 #define SDRAM_CFG_BI                    0x00000001
  43
  44 #ifdef CONFIG_SD_BOOT
  45 #define CONFIG_SPL_MAX_SIZE             0x1a000
  46 #define CONFIG_SPL_STACK                0x1001d000
  47 #define CONFIG_SPL_PAD_TO               0x1c000
  48
  49 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  50                 CONFIG_SYS_MONITOR_LEN)
  51 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  52 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  53 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  54 #define CONFIG_SYS_MONITOR_LEN          0x80000
  55 #endif
  56
  57 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  59
  60 /*
  61  * Serial Port
  62  */
  63 #define CONFIG_SYS_NS16550_SERIAL
  64 #define CONFIG_SYS_NS16550_REG_SIZE     1
  65 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  66
  67 /*
  68  * I2C
  69  */
  70
  71 /* EEPROM */
  72 #define CONFIG_SYS_I2C_EEPROM_NXID
  73 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  74
  75 /*
  76  * MMC
  77  */
  78
  79 /* SATA */
  80 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  81 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  82 #endif
  83 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  84         PCI_DEVICE_ID_FREESCALE_AHCI}
  85
  86 /* SPI */
  87
  88 /*
  89  * eTSEC
  90  */
  91
  92 #ifdef CONFIG_TSEC_ENET
  93 #define CONFIG_MII_DEFAULT_TSEC         1
  94 #define CONFIG_TSEC1                    1
  95 #define CONFIG_TSEC1_NAME               "eTSEC1"
  96 #define CONFIG_TSEC2                    1
  97 #define CONFIG_TSEC2_NAME               "eTSEC2"
  98
  99 #define TSEC1_PHY_ADDR                  1
 100 #define TSEC2_PHY_ADDR                  3
 101
 102 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 103 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 104
 105 #define TSEC1_PHYIDX                    0
 106 #define TSEC2_PHYIDX                    0
 107 #endif
 108
 109 /* PCIe */
 110 #define CONFIG_PCIE1            /* PCIE controler 1 */
 111 #define CONFIG_PCIE2            /* PCIE controler 2 */
 112
 113 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 114
 115 #ifdef CONFIG_PCI
 116 #define CONFIG_PCI_SCAN_SHOW
 117 #endif
 118
 119 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 120 #define CONFIG_LAYERSCAPE_NS_ACCESS
 121 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 122
 123 #define CONFIG_HWCONFIG
 124 #define HWCONFIG_BUFFER_SIZE            256
 125
 126 #define CONFIG_FSL_DEVICE_DISABLE
 127
 128 #define CONFIG_EXTRA_ENV_SETTINGS       \
 129         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 130 "initrd_high=0xffffffff\0"
 131
 132 /*
 133  * Miscellaneous configurable options
 134  */
 135 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 136
 137 #define CONFIG_LS102XA_STREAM_ID
 138
 139 #define CONFIG_SYS_INIT_SP_OFFSET \
 140         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 141 #define CONFIG_SYS_INIT_SP_ADDR \
 142         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 143
 144 #include <asm/fsl_secure_boot.h>
 145
 146 #endif