1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
9 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11 #define CONFIG_SYS_FSL_CLK
14 * Size of malloc() pool
16 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
18 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
19 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
21 #define CONFIG_SYS_CLK_FREQ 100000000
22 #define CONFIG_DDR_CLK_FREQ 100000000
25 * DDR: 800 MHz ( 1600 MT/s data rate )
28 #define DDR_SDRAM_CFG 0x470c0008
29 #define DDR_CS0_BNDS 0x008000bf
30 #define DDR_CS0_CONFIG 0x80014302
31 #define DDR_TIMING_CFG_0 0x50550004
32 #define DDR_TIMING_CFG_1 0xbcb38c56
33 #define DDR_TIMING_CFG_2 0x0040d120
34 #define DDR_TIMING_CFG_3 0x010e1000
35 #define DDR_TIMING_CFG_4 0x00000001
36 #define DDR_TIMING_CFG_5 0x03401400
37 #define DDR_SDRAM_CFG_2 0x00401010
38 #define DDR_SDRAM_MODE 0x00061c60
39 #define DDR_SDRAM_MODE_2 0x00180000
40 #define DDR_SDRAM_INTERVAL 0x18600618
41 #define DDR_DDR_WRLVL_CNTL 0x8655f605
42 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
43 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
44 #define DDR_DDR_CDR1 0x80040000
45 #define DDR_DDR_CDR2 0x00000001
46 #define DDR_SDRAM_CLK_CNTL 0x02000000
47 #define DDR_DDR_ZQ_CNTL 0x89080600
48 #define DDR_CS0_CONFIG_2 0
49 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
50 #define SDRAM_CFG2_D_INIT 0x00000010
51 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
52 #define SDRAM_CFG2_FRC_SR 0x80000000
53 #define SDRAM_CFG_BI 0x00000001
55 #ifdef CONFIG_RAMBOOT_PBL
56 #define CONFIG_SYS_FSL_PBL_PBI \
57 board/freescale/ls1021aiot/ls102xa_pbi.cfg
61 #define CONFIG_SYS_FSL_PBL_RCW \
62 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
63 #define CONFIG_SPL_LIBCOMMON_SUPPORT
64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
65 #define CONFIG_SPL_ENV_SUPPORT
66 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
67 #define CONFIG_SPL_I2C_SUPPORT
68 #define CONFIG_SPL_WATCHDOG_SUPPORT
69 #define CONFIG_SPL_MMC_SUPPORT
70 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
72 #define CONFIG_SPL_TEXT_BASE 0x10000000
73 #define CONFIG_SPL_MAX_SIZE 0x1a000
74 #define CONFIG_SPL_STACK 0x1001d000
75 #define CONFIG_SPL_PAD_TO 0x1c000
77 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
78 CONFIG_SYS_MONITOR_LEN)
79 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
80 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
81 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
82 #define CONFIG_SYS_MONITOR_LEN 0x80000
85 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
91 #define CONFIG_SYS_NS16550_SERIAL
92 #define CONFIG_SYS_NS16550_REG_SIZE 1
93 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
98 #define CONFIG_CMD_I2C
99 #define CONFIG_SYS_I2C
100 #define CONFIG_SYS_I2C_MXC
101 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
102 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
103 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
106 #define CONFIG_ID_EEPROM
107 #define CONFIG_SYS_I2C_EEPROM_NXID
108 #define CONFIG_SYS_EEPROM_BUS_NUM 0
109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
115 #define CONFIG_CMD_MMC
118 #define CONFIG_SCSI_AHCI_PLAT
119 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
120 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
122 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
123 PCI_DEVICE_ID_FREESCALE_AHCI}
125 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
126 #define CONFIG_SYS_SCSI_MAX_LUN 1
127 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
128 CONFIG_SYS_SCSI_MAX_LUN)
131 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
132 #define CONFIG_SPI_FLASH_SPANSION
135 #define QSPI0_AMBA_BASE 0x40000000
136 #define FSL_QSPI_FLASH_SIZE (1 << 24)
137 #define FSL_QSPI_FLASH_NUM 2
138 #define CONFIG_SPI_FLASH_SPANSION
142 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
143 #define CONFIG_CMD_SF
144 #define CONFIG_DM_SPI_FLASH
151 #ifdef CONFIG_TSEC_ENET
152 #define CONFIG_MII_DEFAULT_TSEC 1
153 #define CONFIG_TSEC1 1
154 #define CONFIG_TSEC1_NAME "eTSEC1"
155 #define CONFIG_TSEC2 1
156 #define CONFIG_TSEC2_NAME "eTSEC2"
158 #define TSEC1_PHY_ADDR 1
159 #define TSEC2_PHY_ADDR 3
161 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
162 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
164 #define TSEC1_PHYIDX 0
165 #define TSEC2_PHYIDX 0
167 #define CONFIG_ETHPRIME "eTSEC2"
169 #define CONFIG_PHY_ATHEROS
171 #define CONFIG_HAS_ETH0
172 #define CONFIG_HAS_ETH1
173 #define CONFIG_HAS_ETH2
177 #define CONFIG_PCIE1 /* PCIE controler 1 */
178 #define CONFIG_PCIE2 /* PCIE controler 2 */
180 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
183 #define CONFIG_PCI_SCAN_SHOW
186 #define CONFIG_CMD_MII
188 #define CONFIG_CMDLINE_TAG
190 #define CONFIG_PEN_ADDR_BIG_ENDIAN
191 #define CONFIG_LAYERSCAPE_NS_ACCESS
192 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
193 #define COUNTER_FREQUENCY 12500000
195 #define CONFIG_HWCONFIG
196 #define HWCONFIG_BUFFER_SIZE 256
198 #define CONFIG_FSL_DEVICE_DISABLE
200 #define CONFIG_EXTRA_ENV_SETTINGS \
201 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
202 "initrd_high=0xffffffff\0" \
203 "fdt_high=0xffffffff\0"
206 * Miscellaneous configurable options
208 #define CONFIG_CMD_GREPENV
209 #define CONFIG_CMD_MEMINFO
211 #define CONFIG_SYS_LOAD_ADDR 0x82000000
213 #define CONFIG_LS102XA_STREAM_ID
215 #define CONFIG_SYS_INIT_SP_OFFSET \
216 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
217 #define CONFIG_SYS_INIT_SP_ADDR \
218 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
220 #ifdef CONFIG_SPL_BUILD
221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
223 /* start of monitor */
224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
227 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
233 #define CONFIG_ENV_OVERWRITE
235 #if defined(CONFIG_SD_BOOT)
236 #define CONFIG_ENV_OFFSET 0x100000
237 #define CONFIG_SYS_MMC_ENV_DEV 0
238 #define CONFIG_ENV_SIZE 0x2000
239 #elif defined(CONFIG_QSPI_BOOT)
240 #define CONFIG_ENV_SIZE 0x2000
241 #define CONFIG_ENV_OFFSET 0x100000
242 #define CONFIG_ENV_SECT_SIZE 0x10000
245 #define CONFIG_OF_BOARD_SETUP
246 #define CONFIG_OF_STDOUT_VIA_ALIAS
248 #include <asm/fsl_secure_boot.h>