include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 /*
  14  * DDR: 800 MHz ( 1600 MT/s data rate )
  15  */
  16
  17 #define DDR_SDRAM_CFG                   0x470c0008
  18 #define DDR_CS0_BNDS                    0x008000bf
  19 #define DDR_CS0_CONFIG                  0x80014302
  20 #define DDR_TIMING_CFG_0                0x50550004
  21 #define DDR_TIMING_CFG_1                0xbcb38c56
  22 #define DDR_TIMING_CFG_2                0x0040d120
  23 #define DDR_TIMING_CFG_3                0x010e1000
  24 #define DDR_TIMING_CFG_4                0x00000001
  25 #define DDR_TIMING_CFG_5                0x03401400
  26 #define DDR_SDRAM_CFG_2                 0x00401010
  27 #define DDR_SDRAM_MODE                  0x00061c60
  28 #define DDR_SDRAM_MODE_2                0x00180000
  29 #define DDR_SDRAM_INTERVAL              0x18600618
  30 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  31 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  32 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  33 #define DDR_DDR_CDR1                    0x80040000
  34 #define DDR_DDR_CDR2                    0x00000001
  35 #define DDR_SDRAM_CLK_CNTL              0x02000000
  36 #define DDR_DDR_ZQ_CNTL                 0x89080600
  37 #define DDR_CS0_CONFIG_2                0
  38 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  39 #define SDRAM_CFG2_D_INIT               0x00000010
  40 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  41 #define SDRAM_CFG2_FRC_SR               0x80000000
  42 #define SDRAM_CFG_BI                    0x00000001
  43
  44 #ifdef CONFIG_SD_BOOT
  45 #define CONFIG_SYS_MONITOR_LEN          0x80000
  46 #endif
  47
  48 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  49 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  50
  51 /*
  52  * Serial Port
  53  */
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     1
  56 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  57
  58 /*
  59  * I2C
  60  */
  61
  62 /* EEPROM */
  63 #define CONFIG_SYS_I2C_EEPROM_NXID
  64 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  65
  66 /*
  67  * MMC
  68  */
  69
  70 /* SATA */
  71 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  72 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  73 #endif
  74 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  75         PCI_DEVICE_ID_FREESCALE_AHCI}
  76
  77 /* SPI */
  78
  79 /*
  80  * eTSEC
  81  */
  82
  83 #ifdef CONFIG_TSEC_ENET
  84 #define CONFIG_MII_DEFAULT_TSEC         1
  85 #define CONFIG_TSEC1                    1
  86 #define CONFIG_TSEC1_NAME               "eTSEC1"
  87 #define CONFIG_TSEC2                    1
  88 #define CONFIG_TSEC2_NAME               "eTSEC2"
  89
  90 #define TSEC1_PHY_ADDR                  1
  91 #define TSEC2_PHY_ADDR                  3
  92
  93 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
  94 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
  95
  96 #define TSEC1_PHYIDX                    0
  97 #define TSEC2_PHYIDX                    0
  98 #endif
  99
 100 /* PCIe */
 101 #define CONFIG_PCIE1            /* PCIE controler 1 */
 102 #define CONFIG_PCIE2            /* PCIE controler 2 */
 103
 104 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 105
 106 #ifdef CONFIG_PCI
 107 #define CONFIG_PCI_SCAN_SHOW
 108 #endif
 109
 110 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 111 #define CONFIG_LAYERSCAPE_NS_ACCESS
 112 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 113
 114 #define CONFIG_HWCONFIG
 115 #define HWCONFIG_BUFFER_SIZE            256
 116
 117 #define CONFIG_FSL_DEVICE_DISABLE
 118
 119 #define CONFIG_EXTRA_ENV_SETTINGS       \
 120         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 121 "initrd_high=0xffffffff\0"
 122
 123 /*
 124  * Miscellaneous configurable options
 125  */
 126 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 127
 128 #define CONFIG_LS102XA_STREAM_ID
 129
 130 #include <asm/fsl_secure_boot.h>
 131
 132 #endif