include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #define CONFIG_SYS_CLK_FREQ             100000000
  18
  19 /*
  20  * DDR: 800 MHz ( 1600 MT/s data rate )
  21  */
  22
  23 #define DDR_SDRAM_CFG                   0x470c0008
  24 #define DDR_CS0_BNDS                    0x008000bf
  25 #define DDR_CS0_CONFIG                  0x80014302
  26 #define DDR_TIMING_CFG_0                0x50550004
  27 #define DDR_TIMING_CFG_1                0xbcb38c56
  28 #define DDR_TIMING_CFG_2                0x0040d120
  29 #define DDR_TIMING_CFG_3                0x010e1000
  30 #define DDR_TIMING_CFG_4                0x00000001
  31 #define DDR_TIMING_CFG_5                0x03401400
  32 #define DDR_SDRAM_CFG_2                 0x00401010
  33 #define DDR_SDRAM_MODE                  0x00061c60
  34 #define DDR_SDRAM_MODE_2                0x00180000
  35 #define DDR_SDRAM_INTERVAL              0x18600618
  36 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  37 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  38 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  39 #define DDR_DDR_CDR1                    0x80040000
  40 #define DDR_DDR_CDR2                    0x00000001
  41 #define DDR_SDRAM_CLK_CNTL              0x02000000
  42 #define DDR_DDR_ZQ_CNTL                 0x89080600
  43 #define DDR_CS0_CONFIG_2                0
  44 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  45 #define SDRAM_CFG2_D_INIT               0x00000010
  46 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  47 #define SDRAM_CFG2_FRC_SR               0x80000000
  48 #define SDRAM_CFG_BI                    0x00000001
  49
  50 #ifdef CONFIG_SD_BOOT
  51 #define CONFIG_SPL_MAX_SIZE             0x1a000
  52 #define CONFIG_SPL_STACK                0x1001d000
  53 #define CONFIG_SPL_PAD_TO               0x1c000
  54
  55 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  56                 CONFIG_SYS_MONITOR_LEN)
  57 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  58 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  59 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  60 #define CONFIG_SYS_MONITOR_LEN          0x80000
  61 #endif
  62
  63 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  65
  66 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  67
  68 /*
  69  * Serial Port
  70  */
  71 #define CONFIG_SYS_NS16550_SERIAL
  72 #define CONFIG_SYS_NS16550_REG_SIZE     1
  73 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  74
  75 /*
  76  * I2C
  77  */
  78
  79 /* EEPROM */
  80 #define CONFIG_SYS_I2C_EEPROM_NXID
  81 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  82
  83 /*
  84  * MMC
  85  */
  86
  87 /* SATA */
  88 #define CONFIG_SCSI_AHCI_PLAT
  89 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  90 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  91 #endif
  92 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  93         PCI_DEVICE_ID_FREESCALE_AHCI}
  94
  95 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
  96 #define CONFIG_SYS_SCSI_MAX_LUN         1
  97 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  98                 CONFIG_SYS_SCSI_MAX_LUN)
  99
 100 /* SPI */
 101
 102 /*
 103  * eTSEC
 104  */
 105
 106 #ifdef CONFIG_TSEC_ENET
 107 #define CONFIG_MII_DEFAULT_TSEC         1
 108 #define CONFIG_TSEC1                    1
 109 #define CONFIG_TSEC1_NAME               "eTSEC1"
 110 #define CONFIG_TSEC2                    1
 111 #define CONFIG_TSEC2_NAME               "eTSEC2"
 112
 113 #define TSEC1_PHY_ADDR                  1
 114 #define TSEC2_PHY_ADDR                  3
 115
 116 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 117 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 118
 119 #define TSEC1_PHYIDX                    0
 120 #define TSEC2_PHYIDX                    0
 121
 122 #define CONFIG_ETHPRIME                 "eTSEC2"
 123
 124 #define CONFIG_HAS_ETH0
 125 #define CONFIG_HAS_ETH1
 126 #define CONFIG_HAS_ETH2
 127 #endif
 128
 129 /* PCIe */
 130 #define CONFIG_PCIE1            /* PCIE controler 1 */
 131 #define CONFIG_PCIE2            /* PCIE controler 2 */
 132
 133 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 134
 135 #ifdef CONFIG_PCI
 136 #define CONFIG_PCI_SCAN_SHOW
 137 #endif
 138
 139 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 140 #define CONFIG_LAYERSCAPE_NS_ACCESS
 141 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 142 #define COUNTER_FREQUENCY               12500000
 143
 144 #define CONFIG_HWCONFIG
 145 #define HWCONFIG_BUFFER_SIZE            256
 146
 147 #define CONFIG_FSL_DEVICE_DISABLE
 148
 149 #define CONFIG_EXTRA_ENV_SETTINGS       \
 150         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 151 "initrd_high=0xffffffff\0"
 152
 153 /*
 154  * Miscellaneous configurable options
 155  */
 156 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 157
 158 #define CONFIG_LS102XA_STREAM_ID
 159
 160 #define CONFIG_SYS_INIT_SP_OFFSET \
 161         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 162 #define CONFIG_SYS_INIT_SP_ADDR \
 163         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 164
 165 #ifdef CONFIG_SPL_BUILD
 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 167 #else
 168 /* start of monitor */
 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 170 #endif
 171
 172 #include <asm/fsl_secure_boot.h>
 173
 174 #endif