1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
16 * DDR: 800 MHz ( 1600 MT/s data rate )
19 #define DDR_SDRAM_CFG 0x470c0008
20 #define DDR_CS0_BNDS 0x008000bf
21 #define DDR_CS0_CONFIG 0x80014302
22 #define DDR_TIMING_CFG_0 0x50550004
23 #define DDR_TIMING_CFG_1 0xbcb38c56
24 #define DDR_TIMING_CFG_2 0x0040d120
25 #define DDR_TIMING_CFG_3 0x010e1000
26 #define DDR_TIMING_CFG_4 0x00000001
27 #define DDR_TIMING_CFG_5 0x03401400
28 #define DDR_SDRAM_CFG_2 0x00401010
29 #define DDR_SDRAM_MODE 0x00061c60
30 #define DDR_SDRAM_MODE_2 0x00180000
31 #define DDR_SDRAM_INTERVAL 0x18600618
32 #define DDR_DDR_WRLVL_CNTL 0x8655f605
33 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
34 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
35 #define DDR_DDR_CDR1 0x80040000
36 #define DDR_DDR_CDR2 0x00000001
37 #define DDR_SDRAM_CLK_CNTL 0x02000000
38 #define DDR_DDR_ZQ_CNTL 0x89080600
39 #define DDR_CS0_CONFIG_2 0
40 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
41 #define SDRAM_CFG2_D_INIT 0x00000010
42 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
43 #define SDRAM_CFG2_FRC_SR 0x80000000
44 #define SDRAM_CFG_BI 0x00000001
47 #define CONFIG_SPL_MAX_SIZE 0x1a000
48 #define CONFIG_SPL_STACK 0x1001d000
49 #define CONFIG_SPL_PAD_TO 0x1c000
51 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
52 CONFIG_SYS_MONITOR_LEN)
53 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
54 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
55 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
56 #define CONFIG_SYS_MONITOR_LEN 0x80000
59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
62 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE 1
69 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
76 #define CONFIG_SYS_I2C_EEPROM_NXID
77 #define CONFIG_SYS_EEPROM_BUS_NUM 0
84 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
85 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
87 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
88 PCI_DEVICE_ID_FREESCALE_AHCI}
96 #ifdef CONFIG_TSEC_ENET
97 #define CONFIG_MII_DEFAULT_TSEC 1
98 #define CONFIG_TSEC1 1
99 #define CONFIG_TSEC1_NAME "eTSEC1"
100 #define CONFIG_TSEC2 1
101 #define CONFIG_TSEC2_NAME "eTSEC2"
103 #define TSEC1_PHY_ADDR 1
104 #define TSEC2_PHY_ADDR 3
106 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
107 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
109 #define TSEC1_PHYIDX 0
110 #define TSEC2_PHYIDX 0
112 #define CONFIG_ETHPRIME "eTSEC2"
114 #define CONFIG_HAS_ETH0
115 #define CONFIG_HAS_ETH1
116 #define CONFIG_HAS_ETH2
120 #define CONFIG_PCIE1 /* PCIE controler 1 */
121 #define CONFIG_PCIE2 /* PCIE controler 2 */
123 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
126 #define CONFIG_PCI_SCAN_SHOW
129 #define CONFIG_PEN_ADDR_BIG_ENDIAN
130 #define CONFIG_LAYERSCAPE_NS_ACCESS
131 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
132 #define COUNTER_FREQUENCY 12500000
134 #define CONFIG_HWCONFIG
135 #define HWCONFIG_BUFFER_SIZE 256
137 #define CONFIG_FSL_DEVICE_DISABLE
139 #define CONFIG_EXTRA_ENV_SETTINGS \
140 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
141 "initrd_high=0xffffffff\0"
144 * Miscellaneous configurable options
146 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
148 #define CONFIG_LS102XA_STREAM_ID
150 #define CONFIG_SYS_INIT_SP_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 #define CONFIG_SYS_INIT_SP_ADDR \
153 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
155 #ifdef CONFIG_SPL_BUILD
156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
158 /* start of monitor */
159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
162 #include <asm/fsl_secure_boot.h>