include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 /*
  15  * Size of malloc() pool
  16  */
  17 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  18
  19 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  20 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  21
  22 #define CONFIG_SYS_CLK_FREQ             100000000
  23
  24 /*
  25  * DDR: 800 MHz ( 1600 MT/s data rate )
  26  */
  27
  28 #define DDR_SDRAM_CFG                   0x470c0008
  29 #define DDR_CS0_BNDS                    0x008000bf
  30 #define DDR_CS0_CONFIG                  0x80014302
  31 #define DDR_TIMING_CFG_0                0x50550004
  32 #define DDR_TIMING_CFG_1                0xbcb38c56
  33 #define DDR_TIMING_CFG_2                0x0040d120
  34 #define DDR_TIMING_CFG_3                0x010e1000
  35 #define DDR_TIMING_CFG_4                0x00000001
  36 #define DDR_TIMING_CFG_5                0x03401400
  37 #define DDR_SDRAM_CFG_2                 0x00401010
  38 #define DDR_SDRAM_MODE                  0x00061c60
  39 #define DDR_SDRAM_MODE_2                0x00180000
  40 #define DDR_SDRAM_INTERVAL              0x18600618
  41 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  42 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  43 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  44 #define DDR_DDR_CDR1                    0x80040000
  45 #define DDR_DDR_CDR2                    0x00000001
  46 #define DDR_SDRAM_CLK_CNTL              0x02000000
  47 #define DDR_DDR_ZQ_CNTL                 0x89080600
  48 #define DDR_CS0_CONFIG_2                0
  49 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  50 #define SDRAM_CFG2_D_INIT               0x00000010
  51 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  52 #define SDRAM_CFG2_FRC_SR               0x80000000
  53 #define SDRAM_CFG_BI                    0x00000001
  54
  55 #ifdef CONFIG_SD_BOOT
  56 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  57 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  58 #define CONFIG_SPL_ENV_SUPPORT
  59 #define CONFIG_SPL_I2C
  60 #define CONFIG_SPL_WATCHDOG
  61 #define CONFIG_SPL_MMC_SUPPORT
  62 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  63
  64 #define CONFIG_SPL_MAX_SIZE             0x1a000
  65 #define CONFIG_SPL_STACK                0x1001d000
  66 #define CONFIG_SPL_PAD_TO               0x1c000
  67
  68 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  69                 CONFIG_SYS_MONITOR_LEN)
  70 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  71 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  72 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  73 #define CONFIG_SYS_MONITOR_LEN          0x80000
  74 #endif
  75
  76 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  77 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  78
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  80
  81 /*
  82  * Serial Port
  83  */
  84 #define CONFIG_SYS_NS16550_SERIAL
  85 #define CONFIG_SYS_NS16550_REG_SIZE     1
  86 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  87
  88 /*
  89  * I2C
  90  */
  91
  92 /* EEPROM */
  93 #define CONFIG_SYS_I2C_EEPROM_NXID
  94 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  95
  96 /*
  97  * MMC
  98  */
  99
 100 /* SATA */
 101 #define CONFIG_SCSI_AHCI_PLAT
 102 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
 103 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
 104 #endif
 105 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
 106         PCI_DEVICE_ID_FREESCALE_AHCI}
 107
 108 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 109 #define CONFIG_SYS_SCSI_MAX_LUN         1
 110 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 111                 CONFIG_SYS_SCSI_MAX_LUN)
 112
 113 /* SPI */
 114 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 115 #define CONFIG_SPI_FLASH_SPANSION
 116 #endif
 117
 118 /*
 119  * eTSEC
 120  */
 121
 122 #ifdef CONFIG_TSEC_ENET
 123 #define CONFIG_MII_DEFAULT_TSEC         1
 124 #define CONFIG_TSEC1                    1
 125 #define CONFIG_TSEC1_NAME               "eTSEC1"
 126 #define CONFIG_TSEC2                    1
 127 #define CONFIG_TSEC2_NAME               "eTSEC2"
 128
 129 #define TSEC1_PHY_ADDR                  1
 130 #define TSEC2_PHY_ADDR                  3
 131
 132 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 133 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 134
 135 #define TSEC1_PHYIDX                    0
 136 #define TSEC2_PHYIDX                    0
 137
 138 #define CONFIG_ETHPRIME                 "eTSEC2"
 139
 140 #define CONFIG_HAS_ETH0
 141 #define CONFIG_HAS_ETH1
 142 #define CONFIG_HAS_ETH2
 143 #endif
 144
 145 /* PCIe */
 146 #define CONFIG_PCIE1            /* PCIE controler 1 */
 147 #define CONFIG_PCIE2            /* PCIE controler 2 */
 148
 149 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 150
 151 #ifdef CONFIG_PCI
 152 #define CONFIG_PCI_SCAN_SHOW
 153 #endif
 154
 155 #define CONFIG_CMDLINE_TAG
 156
 157 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 158 #define CONFIG_LAYERSCAPE_NS_ACCESS
 159 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 160 #define COUNTER_FREQUENCY               12500000
 161
 162 #define CONFIG_HWCONFIG
 163 #define HWCONFIG_BUFFER_SIZE            256
 164
 165 #define CONFIG_FSL_DEVICE_DISABLE
 166
 167 #define CONFIG_EXTRA_ENV_SETTINGS       \
 168         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 169 "initrd_high=0xffffffff\0"
 170
 171 /*
 172  * Miscellaneous configurable options
 173  */
 174 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 175
 176 #define CONFIG_LS102XA_STREAM_ID
 177
 178 #define CONFIG_SYS_INIT_SP_OFFSET \
 179         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 180 #define CONFIG_SYS_INIT_SP_ADDR \
 181         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 182
 183 #ifdef CONFIG_SPL_BUILD
 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 185 #else
 186 /* start of monitor */
 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 188 #endif
 189
 190 #define CONFIG_SYS_QE_FW_ADDR   0x67f40000
 191
 192 #define CONFIG_OF_BOARD_SETUP
 193 #define CONFIG_OF_STDOUT_VIA_ALIAS
 194
 195 #include <asm/fsl_secure_boot.h>
 196
 197 #endif