1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
7 #ifndef __LS1012AQDS_H__
8 #define __LS1012AQDS_H__
10 #include "ls1012a_common.h"
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
19 #define CONFIG_FSL_QIXIS
21 #ifdef CONFIG_FSL_QIXIS
22 #define CONFIG_QIXIS_I2C_ACCESS
23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
24 #define QIXIS_LBMAP_BRDCFG_REG 0x04
25 #define QIXIS_LBMAP_SWITCH 6
26 #define QIXIS_LBMAP_MASK 0x08
27 #define QIXIS_LBMAP_SHIFT 0
28 #define QIXIS_LBMAP_DFLTBANK 0x00
29 #define QIXIS_LBMAP_ALTBANK 0x08
30 #define QIXIS_RST_CTL_RESET 0x31
31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
32 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
33 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
39 #define I2C_MUX_PCA_ADDR_PRI 0x77
40 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
41 #define I2C_RETIMER_ADDR 0x18
42 #define I2C_MUX_CH_DEFAULT 0x8
43 #define I2C_MUX_CH_CH7301 0xC
44 #define I2C_MUX_CH5 0xD
45 #define I2C_MUX_CH7 0xF
47 #define I2C_MUX_CH_VOL_MONITOR 0xa
53 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
56 #define CONFIG_SYS_I2C_EEPROM_NXID
57 #define CONFIG_SYS_EEPROM_BUS_NUM 0
60 /* Voltage monitor on channel 2*/
61 #define I2C_VOL_MONITOR_ADDR 0x40
62 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
63 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
64 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
67 #define CONFIG_FSL_DSPI1
69 #define MMAP_DSPI DSPI1_BASE_ADDR
71 #define CONFIG_SYS_DSPI_CTAR0 1
73 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
74 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
75 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
78 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
79 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
80 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
83 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
84 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
85 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
88 #define CONFIG_PCIE1 /* PCIE controller 1 */
90 #define CONFIG_PCI_SCAN_SHOW
92 #undef CONFIG_EXTRA_ENV_SETTINGS
93 #define CONFIG_EXTRA_ENV_SETTINGS \
95 "fdt_addr=0x00f00000\0" \
96 "kernel_addr=0x01000000\0" \
97 "kernelheader_addr=0x600000\0" \
98 "scriptaddr=0x80000000\0" \
99 "scripthdraddr=0x80080000\0" \
100 "fdtheader_addr_r=0x80100000\0" \
101 "kernelheader_addr_r=0x80200000\0" \
102 "kernel_addr_r=0x96000000\0" \
103 "fdt_addr_r=0x90000000\0" \
104 "load_addr=0xa0000000\0" \
105 "kernel_size=0x2800000\0" \
106 "kernelheader_size=0x40000\0" \
107 "console=ttyS0,115200\0" \
109 "boot_scripts=ls1012aqds_boot.scr\0" \
110 "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \
111 "scan_dev_for_boot_part=" \
112 "part list ${devtype} ${devnum} devplist; " \
113 "env exists devplist || setenv devplist 1; " \
114 "for distro_bootpart in ${devplist}; do " \
115 "if fstype ${devtype} " \
116 "${devnum}:${distro_bootpart} " \
117 "bootfstype; then " \
118 "run scan_dev_for_boot; " \
122 "load ${devtype} ${devnum}:${distro_bootpart} " \
123 "${scriptaddr} ${prefix}${script}; " \
124 "env exists secureboot && load ${devtype} " \
125 "${devnum}:${distro_bootpart} " \
126 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
127 "env exists secureboot " \
128 "&& esbc_validate ${scripthdraddr};" \
129 "source ${scriptaddr}\0" \
130 "qspi_bootcmd=echo Trying load from qspi..;" \
131 "sf probe 0:0 && sf read $load_addr " \
132 "$kernel_addr $kernel_size; env exists secureboot " \
133 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
134 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
135 "bootm $load_addr#$board\0"
137 #ifdef CONFIG_TFABOOT
138 #undef QSPI_NOR_BOOTCOMMAND
139 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
140 "env exists secureboot && esbc_halt;"
143 #include <asm/fsl_secure_boot.h>
144 #endif /* __LS1012AQDS_H__ */