1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
7 #ifndef __LS1012AQDS_H__
8 #define __LS1012AQDS_H__
10 #include "ls1012a_common.h"
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
20 #define CONFIG_FSL_QIXIS
22 #ifdef CONFIG_FSL_QIXIS
23 #define CONFIG_QIXIS_I2C_ACCESS
24 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
25 #define QIXIS_LBMAP_BRDCFG_REG 0x04
26 #define QIXIS_LBMAP_SWITCH 6
27 #define QIXIS_LBMAP_MASK 0x08
28 #define QIXIS_LBMAP_SHIFT 0
29 #define QIXIS_LBMAP_DFLTBANK 0x00
30 #define QIXIS_LBMAP_ALTBANK 0x08
31 #define QIXIS_RST_CTL_RESET 0x31
32 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
33 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
34 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
40 #define I2C_MUX_PCA_ADDR_PRI 0x77
41 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
42 #define I2C_RETIMER_ADDR 0x18
43 #define I2C_MUX_CH_DEFAULT 0x8
44 #define I2C_MUX_CH_CH7301 0xC
45 #define I2C_MUX_CH5 0xD
46 #define I2C_MUX_CH7 0xF
48 #define I2C_MUX_CH_VOL_MONITOR 0xa
54 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
57 #define CONFIG_SYS_I2C_EEPROM_NXID
58 #define CONFIG_SYS_EEPROM_BUS_NUM 0
61 /* Voltage monitor on channel 2*/
62 #define I2C_VOL_MONITOR_ADDR 0x40
63 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
64 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
65 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
68 #define CONFIG_FSL_DSPI1
70 #define MMAP_DSPI DSPI1_BASE_ADDR
72 #define CONFIG_SYS_DSPI_CTAR0 1
74 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
75 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
76 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
79 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
80 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
81 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
84 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
85 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
86 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
89 #define CONFIG_PCIE1 /* PCIE controller 1 */
91 #define CONFIG_PCI_SCAN_SHOW
93 #undef CONFIG_EXTRA_ENV_SETTINGS
94 #define CONFIG_EXTRA_ENV_SETTINGS \
96 "fdt_addr=0x00f00000\0" \
97 "kernel_addr=0x01000000\0" \
98 "kernelheader_addr=0x600000\0" \
99 "scriptaddr=0x80000000\0" \
100 "scripthdraddr=0x80080000\0" \
101 "fdtheader_addr_r=0x80100000\0" \
102 "kernelheader_addr_r=0x80200000\0" \
103 "kernel_addr_r=0x96000000\0" \
104 "fdt_addr_r=0x90000000\0" \
105 "load_addr=0xa0000000\0" \
106 "kernel_size=0x2800000\0" \
107 "kernelheader_size=0x40000\0" \
108 "console=ttyS0,115200\0" \
110 "boot_scripts=ls1012aqds_boot.scr\0" \
111 "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \
112 "scan_dev_for_boot_part=" \
113 "part list ${devtype} ${devnum} devplist; " \
114 "env exists devplist || setenv devplist 1; " \
115 "for distro_bootpart in ${devplist}; do " \
116 "if fstype ${devtype} " \
117 "${devnum}:${distro_bootpart} " \
118 "bootfstype; then " \
119 "run scan_dev_for_boot; " \
123 "load ${devtype} ${devnum}:${distro_bootpart} " \
124 "${scriptaddr} ${prefix}${script}; " \
125 "env exists secureboot && load ${devtype} " \
126 "${devnum}:${distro_bootpart} " \
127 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
128 "env exists secureboot " \
129 "&& esbc_validate ${scripthdraddr};" \
130 "source ${scriptaddr}\0" \
131 "qspi_bootcmd=echo Trying load from qspi..;" \
132 "sf probe 0:0 && sf read $load_addr " \
133 "$kernel_addr $kernel_size; env exists secureboot " \
134 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
135 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
136 "bootm $load_addr#$board\0"
138 #ifdef CONFIG_TFABOOT
139 #undef QSPI_NOR_BOOTCOMMAND
140 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
141 "env exists secureboot && esbc_halt;"
144 #include <asm/fsl_secure_boot.h>
145 #endif /* __LS1012AQDS_H__ */