include/configs/ls1012aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2021 NXP
   5  */
   6
   7 #ifndef __LS1012AQDS_H__
   8 #define __LS1012AQDS_H__
   9
  10 #include "ls1012a_common.h"
  11
  12 /* DDR */
  13 #define CONFIG_SYS_SDRAM_SIZE           0x40000000
  14
  15 /*
  16  * QIXIS Definitions
  17  */
  18
  19 #ifdef CONFIG_FSL_QIXIS
  20 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  21 #define QIXIS_LBMAP_BRDCFG_REG          0x04
  22 #define QIXIS_LBMAP_SWITCH              6
  23 #define QIXIS_LBMAP_MASK                0x08
  24 #define QIXIS_LBMAP_SHIFT               0
  25 #define QIXIS_LBMAP_DFLTBANK            0x00
  26 #define QIXIS_LBMAP_ALTBANK             0x08
  27 #define QIXIS_RST_CTL_RESET             0x31
  28 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
  29 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
  30 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
  31 #endif
  32
  33 /*
  34  * I2C bus multiplexer
  35  */
  36 #define I2C_MUX_PCA_ADDR_PRI            0x77
  37 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
  38 #define I2C_RETIMER_ADDR                0x18
  39 #define I2C_MUX_CH_DEFAULT              0x8
  40 #define I2C_MUX_CH_CH7301               0xC
  41 #define I2C_MUX_CH5                     0xD
  42 #define I2C_MUX_CH7                     0xF
  43
  44 #define I2C_MUX_CH_VOL_MONITOR 0xa
  45
  46 /*
  47 * RTC configuration
  48 */
  49 #define RTC
  50 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
  51
  52 /* EEPROM */
  53 #define CONFIG_SYS_I2C_EEPROM_NXID
  54 #define CONFIG_SYS_EEPROM_BUS_NUM    0
  55
  56
  57 /* Voltage monitor on channel 2*/
  58 #define I2C_VOL_MONITOR_ADDR           0x40
  59 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
  60 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
  61 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
  62
  63 /* DSPI */
  64 #define CONFIG_FSL_DSPI1
  65
  66 #define MMAP_DSPI          DSPI1_BASE_ADDR
  67
  68 #define CONFIG_SYS_DSPI_CTAR0   1
  69
  70 #define CONFIG_SYS_DSPI_CTAR1   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  71                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  72                                 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  73                                 DSPI_CTAR_DT(0))
  74
  75 #define CONFIG_SYS_DSPI_CTAR2   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  76                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  77                                 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
  78                                 DSPI_CTAR_DT(0))
  79
  80 #define CONFIG_SYS_DSPI_CTAR3   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  81                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  82                                 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  83                                 DSPI_CTAR_DT(0))
  84
  85 #define CONFIG_PCIE1            /* PCIE controller 1 */
  86
  87 #define CONFIG_PCI_SCAN_SHOW
  88
  89 #undef CONFIG_EXTRA_ENV_SETTINGS
  90 #define CONFIG_EXTRA_ENV_SETTINGS               \
  91         "verify=no\0"                           \
  92         "kernel_addr=0x01000000\0"              \
  93         "kernelheader_addr=0x600000\0"          \
  94         "scriptaddr=0x80000000\0"               \
  95         "scripthdraddr=0x80080000\0"            \
  96         "fdtheader_addr_r=0x80100000\0"         \
  97         "kernelheader_addr_r=0x80200000\0"      \
  98         "kernel_addr_r=0x96000000\0"            \
  99         "fdt_addr_r=0x90000000\0"               \
 100         "load_addr=0xa0000000\0"                \
 101         "kernel_size=0x2800000\0"               \
 102         "kernelheader_size=0x40000\0"           \
 103         "console=ttyS0,115200\0"                \
 104         BOOTENV                                 \
 105         "boot_scripts=ls1012aqds_boot.scr\0"    \
 106         "boot_script_hdr=hdr_ls1012aqds_bs.out\0"       \
 107         "scan_dev_for_boot_part="               \
 108              "part list ${devtype} ${devnum} devplist; "        \
 109              "env exists devplist || setenv devplist 1; "       \
 110              "for distro_bootpart in ${devplist}; do "          \
 111                   "if fstype ${devtype} "                       \
 112                       "${devnum}:${distro_bootpart} "           \
 113                       "bootfstype; then "                       \
 114                       "run scan_dev_for_boot; " \
 115                   "fi; "                        \
 116               "done\0"                          \
 117         "boot_a_script="                                  \
 118                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 119                         "${scriptaddr} ${prefix}${script}; "    \
 120                 "env exists secureboot && load ${devtype} "     \
 121                         "${devnum}:${distro_bootpart} "         \
 122                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 123                         "env exists secureboot "        \
 124                         "&& esbc_validate ${scripthdraddr};"    \
 125                 "source ${scriptaddr}\0"          \
 126         "qspi_bootcmd=echo Trying load from qspi..;"    \
 127                 "sf probe 0:0 && sf read $load_addr "   \
 128                 "$kernel_addr $kernel_size; env exists secureboot "     \
 129                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 130                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 131                 "bootm $load_addr#$board\0"
 132
 133 #ifdef CONFIG_TFABOOT
 134 #undef QSPI_NOR_BOOTCOMMAND
 135 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
 136                              "env exists secureboot && esbc_halt;"
 137 #endif
 138
 139 #include <asm/fsl_secure_boot.h>
 140 #endif /* __LS1012AQDS_H__ */