3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Logotronic DL board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * include/configs/logodl.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38 #define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
47 * select serial console configuration
49 #define CONFIG_FFUART 1 /* we use FFUART */
51 /* allow to overwrite serial and ethaddr */
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_BAUDRATE 19200
55 #undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
57 #define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
58 /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
59 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
60 #include <cmd_confdefs.h>
62 #define CONFIG_BOOTDELAY 3
63 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
64 #define CONFIG_BOOTARGS "console=ttyS0,19200"
65 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
66 #define CONFIG_NETMASK 255.255.255.0
67 #define CONFIG_IPADDR 192.168.1.56
68 #define CONFIG_SERVERIP 192.168.1.2
69 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
70 #define CONFIG_SHOW_BOOT_PROGRESS
72 #define CONFIG_CMDLINE_TAG 1
75 * Miscellaneous configurable options
79 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
80 * used for the RAM copy of the uboot code
83 #define CFG_MALLOC_LEN (256*1024)
85 #define CFG_LONGHELP /* undef to save memory */
86 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
87 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
88 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
89 #define CFG_MAXARGS 16 /* max number of command args */
90 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
92 #define CFG_MEMTEST_START 0x08000000 /* memtest works on */
93 #define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */
95 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
97 #define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */
99 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
100 /* RS: the oscillator is actually 3680130?? */
102 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
104 /* ^^^^^ Memory Speed 99.53 MHz */
105 /* ^^ Run Mode Speed = 2x Mem Speed */
106 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
108 #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
110 /* valid baudrates */
111 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
114 * SMSC91C111 Network Card
117 #define CONFIG_DRIVER_SMC91111 1
118 #define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
119 #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
120 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
121 #undef CONFIG_SHOW_ACTIVITY
122 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
128 * The stack sizes are set up in start.S using the settings below
130 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
131 #ifdef CONFIG_USE_IRQ
132 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
133 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
137 * Physical Memory Map
139 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
140 #define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
141 #define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
143 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
144 #define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
145 #define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
147 #define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
148 #define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
150 #define CFG_FLASH_BASE PHYS_FLASH_1
156 * GP?? == FOOBAR is 0/1
159 #define _BIT0 0x00000001
160 #define _BIT1 0x00000002
161 #define _BIT2 0x00000004
162 #define _BIT3 0x00000008
164 #define _BIT4 0x00000010
165 #define _BIT5 0x00000020
166 #define _BIT6 0x00000040
167 #define _BIT7 0x00000080
169 #define _BIT8 0x00000100
170 #define _BIT9 0x00000200
171 #define _BIT10 0x00000400
172 #define _BIT11 0x00000800
174 #define _BIT12 0x00001000
175 #define _BIT13 0x00002000
176 #define _BIT14 0x00004000
177 #define _BIT15 0x00008000
179 #define _BIT16 0x00010000
180 #define _BIT17 0x00020000
181 #define _BIT18 0x00040000
182 #define _BIT19 0x00080000
184 #define _BIT20 0x00100000
185 #define _BIT21 0x00200000
186 #define _BIT22 0x00400000
187 #define _BIT23 0x00800000
189 #define _BIT24 0x01000000
190 #define _BIT25 0x02000000
191 #define _BIT26 0x04000000
192 #define _BIT27 0x08000000
194 #define _BIT28 0x10000000
195 #define _BIT29 0x20000000
196 #define _BIT30 0x40000000
197 #define _BIT31 0x80000000
200 #define CFG_LED_A_BIT (_BIT18)
201 #define CFG_LED_A_SR GPSR0
202 #define CFG_LED_A_CR GPCR0
204 #define CFG_LED_B_BIT (_BIT16)
205 #define CFG_LED_B_SR GPSR1
206 #define CFG_LED_B_CR GPCR1
209 /* LED A: off, LED B: off */
210 #define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
211 #define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
212 #define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
214 #define CFG_GPCR0_VAL 0x00000000
215 #define CFG_GPCR1_VAL 0x00000000
216 #define CFG_GPCR2_VAL 0x00000000
218 #define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
219 #define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
220 #define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
222 #define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
223 #define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
224 _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
225 #define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
226 _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
227 #define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
228 #define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
229 _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
230 #define CFG_GAFR2_U_VAL (_BIT1)
232 #define CFG_PSSR_VAL (0x20)
237 #define CFG_MSC0_VAL 0x123c2980
238 #define CFG_MSC1_VAL 0x123c2661
239 #define CFG_MSC2_VAL 0x7ff87ff8
242 /* no sdram/pcmcia here */
243 #define CFG_MDCNFG_VAL 0x00000000
244 #define CFG_MDREFR_VAL 0x00000000
245 #define CFG_MDREFR_VAL_100 0x00000000
246 #define CFG_MDMRS_VAL 0x00000000
249 #define SXCNFG_SETTINGS 0x00000000
252 * PCMCIA and CF Interfaces
255 #define CFG_MECR_VAL 0x00000000
256 #define CFG_MCMEM0_VAL 0x00010504
257 #define CFG_MCMEM1_VAL 0x00010504
258 #define CFG_MCATT0_VAL 0x00010504
259 #define CFG_MCATT1_VAL 0x00010504
260 #define CFG_MCIO0_VAL 0x00004715
261 #define CFG_MCIO1_VAL 0x00004715
265 * FLASH and environment organization
267 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
268 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
270 /* timeout values are in ticks */
271 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
272 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
275 #define CFG_ENV_IS_IN_FLASH 1
276 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
277 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
279 #endif /* __CONFIG_H */